src/soc/decoder/power_fieldsn.py

   1 from collections import OrderedDict
   2 from soc.decoder.power_fields import DecodeFields, BitRange
   3 from nmigen import Module, Elaboratable, Signal, Cat
   4 from nmigen.cli import rtlil
   5
   6
   7 class SignalBitRange(BitRange):
   8     def __init__(self, signal):
   9         BitRange.__init__(self)
  10         self.signal = signal
  11
  12     def __getitem__(self, subs):
  13         # *sigh* field numberings are bit-inverted.  PowerISA 3.0B section 1.3.2
  14         width = self.signal.shape()[0]
  15         print (dir(self))
  16         print (self.items())
  17         if isinstance(subs, slice):
  18             res = []
  19             print (subs)
  20             start, stop, step = subs.start, subs.stop, subs.step
  21             if step is None:
  22                 step = 1
  23             if start is None:
  24                 start = 0
  25             if stop is None:
  26                 stop = -1
  27             if start < 0:
  28                 start = len(self) - start - 1
  29             if stop < 0:
  30                 stop = len(self) - stop - 1
  31             print ("range", start, stop, step)
  32             for t in range(start, stop, step):
  33                 k = OrderedDict.__getitem__(self, t)
  34                 print ("t", t, k)
  35                 res.append(self.signal[width-k-1])
  36             return Cat(*res)
  37         else:
  38             k = OrderedDict.__getitem__(self, subs)
  39             return self.signal[width-k-1]
  40
  41         print ("translated", subs, translated)
  42
  43
  44 class SigDecode(Elaboratable):
  45
  46     def __init__(self, width):
  47         self.opcode_in = Signal(width, reset_less=False)
  48         self.df = DecodeFields(SignalBitRange, [self.opcode_in])
  49         self.df.create_specs()
  50         self.x_s = Signal(len(self.df.FormX.S), reset_less=True)
  51         self.x_sh = Signal(len(self.df.FormX.SH), reset_less=True)
  52         self.dq_xs_s = Signal(len(self.df.FormDQ.SX_S), reset_less=True)
  53
  54     def elaborate(self, platform):
  55         m = Module()
  56         comb = m.d.comb
  57         comb += self.x_s.eq(self.df.FormX.S[0])
  58         comb += self.x_sh.eq(self.df.FormX.SH[0:-1])
  59         comb += self.dq_xs_s.eq(self.df.FormDQ.SX_S[0:-1])
  60         return m
  61
  62     def ports(self):
  63         return [self.opcode_in, self.x_s, self.x_sh]
  64
  65 def create_sigdecode():
  66     s = SigDecode(32)
  67     return s
  68
  69 if __name__ == '__main__':
  70     sigdecode = create_sigdecode()
  71     vl = rtlil.convert(sigdecode, ports=sigdecode.ports())
  72     with open("decoder.il", "w") as f:
  73         f.write(vl)
  74