src/soc/decoder/power_regspec_map.py

   1 """regspec_decode
   2
   3 functions for the relationship between regspecs and Decode2Execute1Type
   4
   5 these functions encodes the understanding (relationship) between
   6 Regfiles, Computation Units, and the Power ISA Decoder (PowerDecoder2).
   7
   8 based on the regspec, which contains the register file name and register
   9 name, return a tuple of:
  10
  11 * how the decoder should determine whether the Function Unit needs
  12   access to a given Regport or not
  13 * which Regfile number on that port should be read to get that data
  14 * when it comes to writing: likewise, which Regfile num should be written
  15
  16 Note that some of the port numbering encoding is *unary*.  in the case
  17 of "Full Condition Register", it's a full 8-bit mask of read/write-enables.
  18 This actually matches directly with the XFX field in MTCR, and at
  19 some point that 8-bit mask from the instruction could actually be passed
  20 directly through to full_cr (TODO).
  21
  22 For the INT and CR numbering, these are expressed in binary in the
  23 instruction and need to be converted to unary (1<<read_reg1.data).
  24 Note however that XFX in MTCR is unary-masked!
  25
  26 XER regs are implicitly-encoded (hard-coded) based on whether the
  27 operation has carry or overflow.
  28
  29 FAST regfile is, again, implicitly encoded, back in PowerDecode2, based
  30 on the type of operation (see DecodeB for an example, where fast_out
  31 is set, then carried into read_fast2 in PowerDecode2).
  32
  33 The SPR regfile on the other hand is *binary*-encoded, and, furthermore,
  34 has to be "remapped" to internal SPR Enum indices (see SPRMap in PowerDecode2)
  35 see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
  36 """
  37 from nmigen import Const
  38 from soc.regfile.regfiles import XERRegs, FastRegs, StateRegs
  39 from soc.decoder.power_enums import CryIn
  40
  41
  42 def regspec_decode_read(e, regfile, name):
  43     """regspec_decode_read
  44     """
  45
  46     # INT regfile
  47
  48     if regfile == 'INT':
  49         # Int register numbering is *unary* encoded
  50         if name == 'ra': # RA
  51             return e.read_reg1.ok, e.read_reg1.data
  52         if name == 'rb': # RB
  53             return e.read_reg2.ok, e.read_reg2.data
  54         if name == 'rc': # RS
  55             return e.read_reg3.ok, e.read_reg3.data
  56
  57     # CR regfile
  58
  59     if regfile == 'CR':
  60         # CRRegs register numbering is *unary* encoded
  61         # *sigh*.  numbering inverted on part-CRs.  because POWER.
  62         if name == 'full_cr': # full CR
  63             return e.do.read_cr_whole, 0b11111111
  64         if name == 'cr_a': # CR A
  65             return e.read_cr1.ok, 1<<(7-e.read_cr1.data)
  66         if name == 'cr_b': # CR B
  67             return e.read_cr2.ok, 1<<(7-e.read_cr2.data)
  68         if name == 'cr_c': # CR C
  69             return e.read_cr3.ok, 1<<(7-e.read_cr3.data)
  70
  71     # XER regfile
  72
  73     if regfile == 'XER':
  74         # XERRegs register numbering is *unary* encoded
  75         SO = 1<<XERRegs.SO
  76         CA = 1<<XERRegs.CA
  77         OV = 1<<XERRegs.OV
  78         if name == 'xer_so':
  79             return (e.do.oe.oe[0] & e.do.oe.oe_ok) | e.xer_in, SO
  80         if name == 'xer_ov':
  81             return (e.do.oe.oe[0] & e.do.oe.oe_ok) | e.xer_in, OV
  82         if name == 'xer_ca':
  83             return (e.do.input_carry == CryIn.CA.value) | e.xer_in, CA
  84
  85     # STATE regfile
  86
  87     if regfile == 'STATE':
  88         # STATE register numbering is *unary* encoded
  89         PC = 1<<StateRegs.PC
  90         MSR = 1<<Stateegs.MSR
  91         if name in ['cia', 'nia']:
  92             return Const(1), PC # TODO: detect read-conditions
  93         if name == 'msr':
  94             return Const(1), MSR # TODO: detect read-conditions
  95
  96     # FAST regfile
  97
  98     if regfile == 'FAST':
  99         # FAST register numbering is *unary* encoded
 100         if name == 'fast1':
 101             return e.read_fast1.ok, e.read_fast1.data
 102         if name == 'fast2':
 103             return e.read_fast2.ok, e.read_fast2.data
 104
 105     # SPR regfile
 106
 107     if regfile == 'SPR':
 108         # SPR register numbering is *binary* encoded
 109         if name == 'spr1':
 110             return e.read_spr1.ok, e.read_spr1.data
 111
 112     assert False, "regspec not found %s %s" % (regfile, name)
 113
 114
 115 def regspec_decode_write(e, regfile, name):
 116     """regspec_decode_write
 117     """
 118
 119     # INT regfile
 120
 121     if regfile == 'INT':
 122         # Int register numbering is *unary* encoded
 123         if name == 'o': # RT
 124             return e.write_reg, e.write_reg.data
 125         if name == 'o1': # RA (update mode: LD/ST EA)
 126             return e.write_ea, e.write_ea.data
 127
 128     # CR regfile
 129
 130     if regfile == 'CR':
 131         # CRRegs register numbering is *unary* encoded
 132         # *sigh*.  numbering inverted on part-CRs.  because POWER.
 133         if name == 'full_cr': # full CR
 134             return e.do.write_cr_whole, 0b11111111
 135         if name == 'cr_a': # CR A
 136             return e.write_cr, 1<<(7-e.write_cr.data)
 137
 138     # XER regfile
 139
 140     if regfile == 'XER':
 141         # XERRegs register numbering is *unary* encoded
 142         SO = 1<<XERRegs.SO
 143         CA = 1<<XERRegs.CA
 144         OV = 1<<XERRegs.OV
 145         if name == 'xer_so':
 146             return e.xer_out, SO # hmmm
 147         if name == 'xer_ov':
 148             return e.xer_out, OV # hmmm
 149         if name == 'xer_ca':
 150             return e.xer_out, CA # hmmm
 151
 152     # STATE regfile
 153
 154     if regfile == 'STATE':
 155         # STATE register numbering is *unary* encoded
 156         PC = 1<<StateRegs.PC
 157         MSR = 1<<StateRegs.MSR
 158         if name in ['cia', 'nia']:
 159             return None, PC # hmmm
 160         if name == 'msr':
 161             return None, MSR # hmmm
 162
 163     # FAST regfile
 164
 165     if regfile == 'FAST':
 166         # FAST register numbering is *unary* encoded
 167         if name == 'fast1':
 168             return e.write_fast1, e.write_fast1.data
 169         if name == 'fast2':
 170             return e.write_fast2, e.write_fast2.data
 171
 172     # SPR regfile
 173
 174     if regfile == 'SPR':
 175         # SPR register numbering is *binary* encoded
 176         if name == 'spr1': # SPR1
 177             return e.write_spr, e.write_spr.data
 178
 179     assert False, "regspec not found %s %s" % (regfile, name)
 180