src/soc/experiment/testmem.py

   1 from nmigen import Module, Elaboratable, Memory
   2
   3
   4 class TestMemory(Elaboratable):
   5     def __init__(self, regwid, addrw):
   6         self.ddepth = 1 # regwid //8
   7         depth = (1<<addrw) // self.ddepth
   8         self.mem   = Memory(width=regwid, depth=depth, init=range(0, depth))
   9         self.rdport = self.mem.read_port() # not now transparent=False)
  10         self.wrport = self.mem.write_port()
  11
  12     def elaborate(self, platform):
  13         m = Module()
  14         m.submodules.rdport = self.rdport
  15         m.submodules.wrport = self.wrport
  16         return m