add extra pipeline stages to ALU FU to make timing
[soc.git] / src / soc / fu / alu / pipeline.py
1 from nmutil.singlepipe import ControlBase
2 from nmutil.pipemodbase import PipeModBaseChain
3 from soc.fu.alu.input_stage import ALUInputStage
4 from soc.fu.alu.main_stage import ALUMainStage
5 from soc.fu.alu.output_stage import ALUOutputStage
6
7
8 class ALUStages(PipeModBaseChain):
9 def get_chain(self):
10 inp = ALUInputStage(self.pspec)
11 main = ALUMainStage(self.pspec)
12 out = ALUOutputStage(self.pspec)
13 return [inp, main, out]
14
15
16 class ALUBasePipe(ControlBase):
17 def __init__(self, pspec):
18 ControlBase.__init__(self)
19 self.pspec = pspec
20 self.pipe1 = ALUStages(pspec)
21 self._eqs = self.connect([self.pipe1])
22
23 def elaborate(self, platform):
24 m = ControlBase.elaborate(self, platform)
25 m.submodules.pipe1 = self.pipe1
26 m.d.comb += self._eqs
27 return m
28
29 class ALUStages1(PipeModBaseChain):
30 def get_chain(self):
31 inp = ALUInputStage(self.pspec)
32 return [inp]
33
34 class ALUStages2(PipeModBaseChain):
35 def get_chain(self):
36 main = ALUMainStage(self.pspec)
37 return [main]
38
39
40 class ALUStages3(PipeModBaseChain):
41 def get_chain(self):
42 out = ALUOutputStage(self.pspec)
43 return [out]
44
45
46 class ALUBasePipe(ControlBase):
47 def __init__(self, pspec):
48 ControlBase.__init__(self)
49 self.pspec = pspec
50 self.pipe1 = ALUStages1(pspec)
51 self.pipe2 = ALUStages2(pspec)
52 self.pipe3 = ALUStages3(pspec)
53 self._eqs = self.connect([self.pipe1, self.pipe2, self.pipe3])
54
55 def elaborate(self, platform):
56 m = ControlBase.elaborate(self, platform)
57 m.submodules.logical_pipe1 = self.pipe1
58 m.submodules.logical_pipe2 = self.pipe2
59 m.submodules.logical_pipe3 = self.pipe3
60 m.d.comb += self._eqs
61 return m
62