src/soc/fu/logical/pipe_data.py

   1 from soc.fu.pipe_data import FUBaseData
   2 from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
   3 from soc.fu.logical.logical_input_record import CompLogicalOpSubset
   4
   5
   6 # input (and output) for logical initial stage (common input)
   7 class LogicalInputData(FUBaseData):
   8     def __init__(self, pspec):
   9         super().__init__(pspec, False)
  10         # convenience
  11         self.a, self.b = self.ra, self.rb
  12
  13     @property
  14     def regspec(self):
  15         return [('INT', 'ra', self.intrange),  # RA
  16                ('INT', 'rb', self.intrange),  # RB/immediate
  17                ('XER', 'xer_so', '32'),    # bit0: so
  18                ]
  19
  20 # input to logical final stage (common output)
  21 class LogicalOutputData(FUBaseData):
  22     def __init__(self, pspec):
  23         super().__init__(pspec, True)
  24         # convenience
  25         self.cr0 = self.cr_a
  26
  27     @property
  28     def regspec(self):
  29         return [('INT', 'o', self.intrange),
  30                ('CR', 'cr_a', '0:3'),
  31                ('XER', 'xer_so', '32'),    # bit0: so
  32                ]
  33
  34
  35 # output from logical final stage (common output) - note that XER.so
  36 # is *not* included (the only reason it's in the input is because of CR0)
  37 class LogicalOutputDataFinal(FUBaseData):
  38     def __init__(self, pspec):
  39         super().__init__(pspec, True)
  40         # convenience
  41         self.cr0 = self.cr_a
  42     @property
  43     def regspec(self):
  44         return [('INT', 'o', self.intrange),
  45                ('CR', 'cr_a', '0:3'),
  46                ]
  47
  48
  49 class LogicalPipeSpec(CommonPipeSpec):
  50     regspecklses = (LogicalInputData, LogicalOutputDataFinal)
  51     opsubsetkls = CompLogicalOpSubset