1 from soc
.fu
.pipe_data
import FUBaseData
2 from soc
.fu
.alu
.pipe_data
import ALUOutputData
, CommonPipeSpec
3 from soc
.fu
.logical
.logical_input_record
import CompLogicalOpSubset
6 # input (and output) for logical initial stage (common input)
7 class LogicalInputData(FUBaseData
):
8 regspec
= [('INT', 'ra', '0:63'), # RA
9 ('INT', 'rb', '0:63'), # RB/immediate
10 ('XER', 'xer_so', '32'), # bit0: so
12 def __init__(self
, pspec
):
13 super().__init
__(pspec
, False)
15 self
.a
, self
.b
= self
.ra
, self
.rb
18 # input to logical final stage (common output)
19 class LogicalOutputData(FUBaseData
):
20 regspec
= [('INT', 'o', '0:63'), # RT
21 ('CR', 'cr_a', '0:3'),
22 ('XER', 'xer_so', '32'), # bit0: so
24 def __init__(self
, pspec
):
25 super().__init
__(pspec
, True)
30 # output from logical final stage (common output) - note that XER.so
31 # is *not* included (the only reason it's in the input is because of CR0)
32 class LogicalOutputDataFinal(FUBaseData
):
33 regspec
= [('INT', 'o', '0:63'), # RT
34 ('CR', 'cr_a', '0:3'),
36 def __init__(self
, pspec
):
37 super().__init
__(pspec
, True)
42 class LogicalPipeSpec(CommonPipeSpec
):
43 regspecklses
= (LogicalInputData
, LogicalOutputDataFinal
)
44 opsubsetkls
= CompLogicalOpSubset