1 """MMU Pipeline Data structures
3 Covers MFMMU and MTMMU for MMU MMUs (dsisr, dar), and DCBZ and TLBIE.
5 Interestingly none of the MMU instructions use RA, they all use RB.
6 except dcbz which uses (RA|0)
9 * https://bugs.libre-soc.org/show_bug.cgi?id=491
10 * https://libre-soc.org/3d_gpu/architecture/regfile/
13 from soc
.fu
.pipe_data
import FUBaseData
14 from soc
.fu
.mmu
.mmu_input_record
import CompMMUOpSubset
15 from soc
.fu
.alu
.pipe_data
import CommonPipeSpec
16 from openpower
.exceptions
import LDSTException
19 class MMUInputData(FUBaseData
):
20 regspec
= [('INT', 'ra', '0:63'), # RA
21 ('INT', 'rb', '0:63'), # RB
22 ('SPR', 'spr1', '0:63'), # MMU (slow)
24 def __init__(self
, pspec
):
25 super().__init
__(pspec
, False)
31 class MMUOutputData(FUBaseData
):
32 regspec
= [('INT', 'o', '0:63'), # RT
33 ('SPR', 'spr1', '0:63'), # MMU (slow)
35 def __init__(self
, pspec
):
36 super().__init
__(pspec
, True, LDSTException
)
39 class MMUPipeSpec(CommonPipeSpec
):
40 regspecklses
= (MMUInputData
, MMUOutputData
)
41 opsubsetkls
= CompMMUOpSubset