src/soc/fu/shift_rot/test/test_maskgen.py

   1 from nmigen import Signal, Module
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 from soc.fu.shift_rot.maskgen import MaskGen
   6 from openpower.decoder.helpers import ISACallerHelper
   7 import random
   8 import unittest
   9
  10 class MaskGenTestCase(FHDLTestCase):
  11     def test_maskgen(self):
  12         MASK = ISACallerHelper(64, FPSCR=None).MASK
  13         m = Module()
  14         comb = m.d.comb
  15         m.submodules.dut = dut = MaskGen(64)
  16         mb = Signal.like(dut.mb)
  17         me = Signal.like(dut.me)
  18         o = Signal.like(dut.o)
  19
  20         comb += [
  21             dut.mb.eq(mb),
  22             dut.me.eq(me),
  23             o.eq(dut.o)]
  24
  25         sim = Simulator(m)
  26
  27         def process():
  28             for x in range(0, 64):
  29                 for y in range(0, 64):
  30                     yield mb.eq(x)
  31                     yield me.eq(y)
  32                     yield Delay(1e-6)
  33
  34                     expected = MASK(x, y)
  35                     result = yield o
  36                     self.assertEqual(expected, result)
  37
  38         sim.add_process(process) # or sim.add_sync_process(process), see below
  39         with sim.write_vcd("maskgen.vcd", "maskgen.gtkw", traces=dut.ports()):
  40             sim.run()
  41
  42     def test_ilang(self):
  43         dut = MaskGen(64)
  44         vl = rtlil.convert(dut, ports=dut.ports())
  45         with open("maskgen.il", "w") as f:
  46             f.write(vl)
  47
  48 if __name__ == '__main__':
  49     unittest.main()