src/soc/simple/issuer_verilog.py

   1 """simple core issuer verilog generator
   2 """
   3
   4 import argparse
   5 from nmigen.cli import verilog
   6
   7 from openpower.consts import MSR
   8 from soc.config.test.test_loadstore import TestMemPspec
   9 from soc.simple.issuer import TestIssuer, TestIssuerInternal
  10
  11
  12 if __name__ == '__main__':
  13     parser = argparse.ArgumentParser(description="Simple core issuer " \
  14                                      "verilog generator")
  15     parser.add_argument("output_filename")
  16     parser.add_argument("--enable-xics", dest='xics', action="store_true",
  17                         help="Enable interrupts",
  18                         default=True)
  19     parser.add_argument("--disable-xics", dest='xics', action="store_false",
  20                         help="Disable interrupts",
  21                         default=False)
  22     parser.add_argument("--enable-lessports", dest='lessports',
  23                         action="store_true",
  24                         help="Enable less regfile ports",
  25                         default=True)
  26     parser.add_argument("--disable-lessports", dest='lessports',
  27                         action="store_false",
  28                         help="enable more regfile ports",
  29                         default=False)
  30     parser.add_argument("--enable-core", dest='core', action="store_true",
  31                         help="Enable main core",
  32                         default=True)
  33     parser.add_argument("--disable-core", dest='core', action="store_false",
  34                         help="disable main core",
  35                         default=False)
  36     parser.add_argument("--enable-mmu", dest='mmu', action="store_true",
  37                         help="Enable mmu",
  38                         default=False)
  39     parser.add_argument("--disable-mmu", dest='mmu', action="store_false",
  40                         help="Disable mmu",
  41                         default=False)
  42     parser.add_argument("--enable-pll", dest='pll', action="store_true",
  43                         help="Enable pll",
  44                         default=False)
  45     parser.add_argument("--disable-pll", dest='pll', action="store_false",
  46                         help="Disable pll",
  47                         default=False)
  48     parser.add_argument("--enable-testgpio", action="store_true",
  49                         help="Disable gpio pins",
  50                         default=False)
  51     parser.add_argument("--enable-sram4x4kblock", action="store_true",
  52                         help="Disable sram 4x4k block",
  53                         default=False)
  54     parser.add_argument("--debug", default="jtag", help="Select debug " \
  55                         "interface [jtag | dmi] [default jtag]")
  56     parser.add_argument("--enable-svp64", dest='svp64', action="store_true",
  57                         help="Enable SVP64",
  58                         default=True)
  59     parser.add_argument("--disable-svp64", dest='svp64', action="store_false",
  60                         help="disable SVP64",
  61                         default=False)
  62     parser.add_argument("--pc-reset", default="0",
  63                         help="Set PC at reset (default 0)")
  64     parser.add_argument("--xlen", default=64, type=int,
  65                         help="Set register width [default 64]")
  66     # create a module that's directly compatible as a drop-in replacement
  67     # in microwatt.v
  68     parser.add_argument("--microwatt-compat", dest='mwcompat',
  69                         action="store_true",
  70                         help="generate microwatt-compatible interface",
  71                         default=False)
  72     parser.add_argument("--old-microwatt-compat", dest='old_mwcompat',
  73                         action="store_true",
  74                         help="generate old microwatt-compatible interface",
  75                         default=True)
  76     parser.add_argument("--microwatt-debug", dest='mwdebug',
  77                         action="store_true",
  78                         help="generate old microwatt-compatible interface",
  79                         default=False)
  80     # small cache option
  81     parser.add_argument("--small-cache", dest='smallcache',
  82                         action="store_true",
  83                         help="generate small caches",
  84                         default=False)
  85
  86     # allow overlaps in TestIssuer
  87     parser.add_argument("--allow-overlap", dest='allow_overlap',
  88                         action="store_true",
  89                         help="allow overlap in TestIssuer",
  90                         default=False)
  91
  92     args = parser.parse_args()
  93
  94     # convenience: set some defaults
  95     if args.mwcompat:
  96         args.pll = False
  97         args.debug = 'dmi'
  98         args.core = True
  99         args.xics = False
 100         args.gpio = False
 101         args.sram4x4kblock = False
 102         args.svp64 = False
 103
 104     print(args)
 105
 106     units = {'alu': 1,
 107              'cr': 1, 'branch': 1, 'trap': 1,
 108              'logical': 1,
 109              'spr': 1,
 110              'div': 1,
 111              'mul': 1,
 112              'shiftrot': 1
 113             }
 114     if args.mmu:
 115         units['mmu'] = 1 # enable MMU
 116
 117     # decide which memory type to configure
 118     if args.mmu:
 119         ldst_ifacetype = 'mmu_cache_wb'
 120         imem_ifacetype = 'mmu_cache_wb'
 121     else:
 122         ldst_ifacetype = 'bare_wb'
 123         imem_ifacetype = 'bare_wb'
 124
 125     # default MSR
 126     msr_reset = (1<<MSR.LE) | (1<<MSR.SF) # 64-bit, little-endian default
 127
 128     # default PC
 129     if args.pc_reset.startswith("0x"):
 130         pc_reset = int(args.pc_reset, 16)
 131     else:
 132         pc_reset = int(args.pc_reset)
 133
 134     pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
 135                          imem_ifacetype=imem_ifacetype,
 136                          addr_wid=64,
 137                          mask_wid=8,
 138                          # pipeline and integer register file width
 139                          XLEN=args.xlen,
 140                          # must leave at 64
 141                          reg_wid=64,
 142                          # set to 32 for instruction-memory width=32
 143                          imem_reg_wid=64,
 144                          # set to 32 to make data wishbone bus 32-bit
 145                          #wb_data_wid=32,
 146                          xics=args.xics, # XICS interrupt controller
 147                          nocore=not args.core, # test coriolis2 ioring
 148                          regreduce = args.lessports, # less regfile ports
 149                          use_pll=args.pll,  # bypass PLL
 150                          gpio=args.enable_testgpio, # for test purposes
 151                          sram4x4kblock=args.enable_sram4x4kblock, # add SRAMs
 152                          debug=args.debug,      # set to jtag or dmi
 153                          svp64=args.svp64,      # enable SVP64
 154                          microwatt_mmu=args.mmu,         # enable MMU
 155                          microwatt_compat=args.mwcompat, # microwatt compatible
 156                          microwatt_old=args.old_mwcompat, # old microwatt api
 157                          microwatt_debug=args.mwdebug, # microwatt debug signals
 158                          small_cache=args.smallcache, # small cache/TLB sizes
 159                          allow_overlap=args.allow_overlap, # allow overlap
 160                          units=units,
 161                          msr_reset=msr_reset,
 162                          pc_reset=pc_reset)
 163     #if args.mwcompat:
 164     #    pspec.core_domain = 'sync'
 165
 166     print("mmu", pspec.__dict__["microwatt_mmu"])
 167     print("nocore", pspec.__dict__["nocore"])
 168     print("regreduce", pspec.__dict__["regreduce"])
 169     print("gpio", pspec.__dict__["gpio"])
 170     print("sram4x4kblock", pspec.__dict__["sram4x4kblock"])
 171     print("xics", pspec.__dict__["xics"])
 172     print("use_pll", pspec.__dict__["use_pll"])
 173     print("debug", pspec.__dict__["debug"])
 174     print("SVP64", pspec.__dict__["svp64"])
 175     print("XLEN", pspec.__dict__["XLEN"])
 176     print("MSR@reset", hex(pspec.__dict__["msr_reset"]))
 177     print("PC@reset", hex(pspec.__dict__["pc_reset"]))
 178     print("Microwatt compatibility", pspec.__dict__["microwatt_compat"])
 179     print("Old Microwatt compatibility", pspec.__dict__["microwatt_old"])
 180     print("Microwatt debug", pspec.__dict__["microwatt_debug"])
 181     print("Small Cache/TLB", pspec.__dict__["small_cache"])
 182
 183     if args.mwcompat:
 184         dut = TestIssuerInternal(pspec)
 185         name = "external_core_top"
 186     else:
 187         dut = TestIssuer(pspec)
 188         name = "test_issuer"
 189
 190     vl = verilog.convert(dut, ports=dut.external_ports(), name=name)
 191     with open(args.output_filename, "w") as f:
 192         f.write(vl)