add syn_ramstyle "block_ram" attributes and reduce i/d-cache sizes again

[soc.git] / src / soc / experiment / icache.py

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 8e457be57a8083d30951d109cc4d47efca95edc0..6ed9ed4458aa71a8977a9a507c3c1c34db9bde51 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -339,7 +339,7 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
             # reduce way sizes and num lines
             ICacheConfig.__init__(self, NUM_LINES = 4,
                                         NUM_WAYS = 1,
-                                        TLB_SIZE=16 # needs device-tree update
+                                        TLB_SIZE=4 # needs device-tree update
                                  )
         else:
             ICacheConfig.__init__(self)