add litex wishbone interconnect to 4x 4k SRAMs

[soc.git] / src / soc / litex / florent / Makefile

diff --git a/src/soc/litex/florent/Makefile b/src/soc/litex/florent/Makefile
index d1c5cc1de0ba7de83fb19a827cc20202bb3fdbf0..ab73b7bfa8573213d5497d5316565abb72c98d60 100644 (file)
--- a/src/soc/litex/florent/Makefile
+++ b/src/soc/litex/florent/Makefile
@@ -5,6 +5,7 @@ ls180:
        cp build/ls180/gateware/mem_1.init .
        cp build/ls180/gateware/mem_2.init .
        cp build/ls180/gateware/mem_3.init .
+       cp build/ls180/gateware/mem_4.init .
        cp libresoc/libresoc.v .
        yosys -p 'read_verilog libresoc.v' \
           -p 'write_ilang libresoc_cvt.il'