add litex wishbone interconnect to 4x 4k SRAMs

[soc.git] / src / soc / litex / florent / libresoc / core.py

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 55a84c97a6606c982aedc700627c009b0830893a..189216e241b0ec5fbd51a3bce826edc376f11c5e 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -187,6 +187,11 @@ class LibreSoC(CPU):
         if jtag_en:
             self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
 
+        if "sram4k" in variant or variant == 'ls180':
+            self.srams = srams = []
+            for i in range(4):
+                srams.append(wb.Interface(data_width=64, adr_width=29))
+
         self.periph_buses = [ibus, dbus]
         self.memory_buses = []
 
@@ -261,6 +266,10 @@ class LibreSoC(CPU):
             self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
         if jtag_en:
             self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
+        if "sram4k" in variant or variant == 'ls180':
+            for i, sram in enumerate(srams):
+                self.cpu_params.update(make_wb_slave("sram4k_%d_wb" % i, sram))
+
         # and set ibus advanced tags to zero (disable)
         self.cpu_params['i_ibus__cti'] = 0
         self.cpu_params['i_ibus__bte'] = 0