versa_ecp5 adds ability to build and load for ulx3s85f, fixes testgpio

[soc.git] / src / soc / simple / issuer_verilog.py

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 92ec2f54a25815ec82e7c7948c6a47a1d785610b..c9483be22857c6c983933c1d4f9c1c52b27b1aae 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -38,6 +38,7 @@ if __name__ == '__main__':
              'mul': 1,
              'shiftrot': 1
             }
+
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
                          imem_ifacetype='bare_wb',
                          addr_wid=48,
@@ -55,6 +56,12 @@ if __name__ == '__main__':
                          debug=args.debug,      # set to jtag or dmi
                          units=units)
 
+    print("nocore", pspec.__dict__["nocore"])
+    print("gpio", pspec.__dict__["gpio"])
+    print("xics", pspec.__dict__["xics"])
+    print("use_pll", pspec.__dict__["use_pll"])
+    print("debug", pspec.__dict__["debug"])
+
     dut = TestIssuer(pspec)
 
     vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")