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nope, default features in Tercel WB Buses need to not set err yet
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 30 Mar 2022 09:27:44 +0000
(10:27 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 30 Mar 2022 09:27:44 +0000
(10:27 +0100)
src/soc/bus/tercel.py
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diff --git
a/src/soc/bus/tercel.py
b/src/soc/bus/tercel.py
index 102218236a5faa2830ff8e83395798fc741b7aa2..328bf661d374589f7fefc859467b55e7e9597e9f 100644
(file)
--- a/
src/soc/bus/tercel.py
+++ b/
src/soc/bus/tercel.py
@@
-50,7
+50,8
@@
class Tercel(Elaboratable):
# set up the wishbone busses
if features is None:
# set up the wishbone busses
if features is None:
- features = frozenset({'err'})
+ #features = frozenset({'err'}) # sigh
+ features = frozenset()
if bus is None:
bus = Interface(addr_width=spi_region_addr_width,
data_width=data_width,
if bus is None:
bus = Interface(addr_width=spi_region_addr_width,
data_width=data_width,
@@
-138,7
+139,7
@@
class Tercel(Elaboratable):
i_wishbone_stb=bus.stb,
i_wishbone_cyc=bus.cyc,
o_wishbone_ack=bus.ack,
i_wishbone_stb=bus.stb,
i_wishbone_cyc=bus.cyc,
o_wishbone_ack=bus.ack,
- o_wishbone_err=bus.err,
+
#
o_wishbone_err=bus.err,
# Configuration region Wishbone bus signals
i_cfg_wishbone_adr=cfg_bus.adr,
# Configuration region Wishbone bus signals
i_cfg_wishbone_adr=cfg_bus.adr,
@@
-149,7
+150,7
@@
class Tercel(Elaboratable):
i_cfg_wishbone_stb=cfg_bus.stb,
i_cfg_wishbone_cyc=cfg_bus.cyc,
o_cfg_wishbone_ack=cfg_bus.ack,
i_cfg_wishbone_stb=cfg_bus.stb,
i_cfg_wishbone_cyc=cfg_bus.cyc,
o_cfg_wishbone_ack=cfg_bus.ack,
- o_cfg_wishbone_err=cfg_bus.err,
+
#
o_cfg_wishbone_err=cfg_bus.err,
# QSPI signals
o_spi_d_out=self.dq_out,
# QSPI signals
o_spi_d_out=self.dq_out,