| 2022-03-30 |
Luke Kenneth Casson... | nope, default features in Tercel WB Buses need to not...
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commit | commitdiff | tree |
| 2022-03-29 |
Luke Kenneth Casson... | add bus.err to list of default Wishbone signals in...
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commit | commitdiff | tree |
| 2022-03-29 |
Luke Kenneth Casson... | byte-reverse Tercel read/write data and config bus...
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commit | commitdiff | tree |
| 2022-03-29 |
Luke Kenneth Casson... | set clock freq Constant length to 32-bit in Tercel.
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commit | commitdiff | tree |
| 2022-03-29 |
Luke Kenneth Casson... | self.specials does not exist, Instances must be added...
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commit | commitdiff | tree |
| 2022-03-29 |
Luke Kenneth Casson... | more sorting out wishbone names in Tercel
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commit | commitdiff | tree |
| 2022-03-29 |
Luke Kenneth Casson... | fix names of Instance signals in Tercel
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commit | commitdiff | tree |
| 2022-03-29 |
Luke Kenneth Casson... | sort out variable names in Tercel
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commit | commitdiff | tree |
| 2022-03-29 |
Luke Kenneth Casson... | self.comb does not exist, comb is a local temp-var...
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commit | commitdiff | tree |
| 2022-03-29 |
Luke Kenneth Casson... | whitespace cleanup (80 char limit)
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commit | commitdiff | tree |
| 2022-03-26 |
Luke Kenneth Casson... | rename PLRU modules to avoid conflict in microwatt
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commit | commitdiff | tree |
| 2022-03-18 |
Luke Kenneth Casson... | whitespace cleanup (80 char limit, pep8)
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commit | commitdiff | tree |
| 2022-03-18 |
Luke Kenneth Casson... | turn CompALU/CompLDST latches synchronous
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commit | commitdiff | tree |
| 2022-03-12 |
Luke Kenneth Casson... | add extra pipeline stages to ALU FU to make timing
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commit | commitdiff | tree |
| 2022-03-12 |
Luke Kenneth Casson... | introduce extra register of delay to split combinatorial...
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commit | commitdiff | tree |
| 2022-03-12 |
Luke Kenneth Casson... | Revert "read last row from r.wb.adr not r.req_adr in...
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commit | commitdiff | tree |
| 2022-03-12 |
Luke Kenneth Casson... | Revert "store cur_state.pc+4 in separate register to...
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commit | commitdiff | tree |
| 2022-03-12 |
Luke Kenneth Casson... | store cur_state.pc+4 in separate register to help reduce
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commit | commitdiff | tree |
| 2022-03-12 |
Luke Kenneth Casson... | read last row from r.wb.adr not r.req_adr in icache
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commit | commitdiff | tree |
| 2022-03-08 |
Luke Kenneth Casson... | remove stbs_done in icache.py
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commit | commitdiff | tree |
| 2022-03-08 |
Luke Kenneth Casson... | remove ld_stbs_done from dcache: not needed
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commit | commitdiff | tree |
| 2022-03-08 |
Luke Kenneth Casson... | work-in-progress on sdram opencores wrapper
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commit | commitdiff | tree |
| 2022-02-28 |
Luke Kenneth Casson... | attempting to introduce an extra few clock cycles delay...
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commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | for lulz make I-Cache possible to set to 32-bit (XLEN=32)
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commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | bit_length is 1 more than needed: subtract 1 from XLEN...
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commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | fix up shift_rot test_pipe_caller to new regspeckls...
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commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | convert shift_rot pipeline to XLEN=32/64
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commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | fix up Logical pipeline to produce HDL with XLEN=32
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commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | whoops ALU common output target must be XLEN-bit,
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commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | set up dummy parent_pspec to pass XLEN=64 in
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commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | start on converting MUL and DIV pipelines to XLEN
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commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | convert from public static functions/properties for...
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commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | fix ALU with XLEN=32, carry and overflow
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commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | use XLEN in Function Units (starting with ALU)
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commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | add XLEN to issuer_verilog.py defaults to 64
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commit | commitdiff | tree |
| 2022-02-27 |
Luke Kenneth Casson... | add XLEN option to regfiles via pspec
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commit | commitdiff | tree |
| 2022-02-23 |
Luke Kenneth Casson... | forgot to pass cix (cache-inhibited) through to LD...
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commit | commitdiff | tree |
| 2022-02-21 |
Luke Kenneth Casson... | again reduce combinatorial chains, similar to Trap...
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commit | commitdiff | tree |
| 2022-02-20 |
Luke Kenneth Casson... | add syn_ramstyle "block_ram" attributes and reduce...
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commit | commitdiff | tree |
| 2022-02-20 |
Luke Kenneth Casson... | same as shiftrot, split out separate pipelines for...
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commit | commitdiff | tree |
| 2022-02-20 |
Luke Kenneth Casson... | put LDST go-store on a 1-clock delay to help with combinator...
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commit | commitdiff | tree |
| 2022-02-20 |
Luke Kenneth Casson... | name core_stop and terminated_o synchronous to potentially...
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commit | commitdiff | tree |
| 2022-02-20 |
Luke Kenneth Casson... | nope, it's perfectly fine
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commit | commitdiff | tree |
| 2022-02-20 |
Luke Kenneth Casson... | weird exception, oe not found in the shiftrot input...
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commit | commitdiff | tree |
| 2022-02-20 |
Luke Kenneth Casson... | separate out shiftrot stages due to size of main stage...
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commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | add blockram style to regfile Memory
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commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | use block_ram attribute for FPGA synthesis
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commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | reduce number of d-cache lines in microwatt fpga mode
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commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | couple of adjustments to reduce gate count in i/d-cache
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commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | add SDRAM Configuration Record
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commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | reduce TLB set size from 64 to 16 to get FPGA resource...
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commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | drastically reduce I-Cache size in microwatt-compat...
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commit | commitdiff | tree |
| 2022-02-18 |
Luke Kenneth Casson... | parameterise I-Cache similar to D-Cache. lots of "self."
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commit | commitdiff | tree |
| 2022-02-17 |
Luke Kenneth Casson... | add opencores SDRAM verilog wrapper
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commit | commitdiff | tree |
| 2022-02-16 |
Luke Kenneth Casson... | oof. big update to DCache to accept config parameters
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commit | commitdiff | tree |
| 2022-02-16 |
Luke Kenneth Casson... | connect UART16550 pins if given
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commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | for *write* the counter-address on downconvert was...
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commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | add wishbone downconvert "skip" of slave sel so that...
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commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | add SysCon reg_info, has uart and has large SYSCON
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commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | sigh, stall was not working but actually turns out...
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commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | add option to specify UART16550 width (32/8)
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commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | add beginnings of syscon bus peripheral
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commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | update comments
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commit | commitdiff | tree |
| 2022-02-15 |
Luke Kenneth Casson... | resolve WBDownConvert ack issues when stall is active
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commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | strip first 3 bits of WB address from microwatt d/i...
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commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | slave sends stall signal, master receives, in
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commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | sort out ExternalCore signal names
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commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | add wishbone slave signal to downconvert if present
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commit | commitdiff | tree |
| 2022-02-14 |
Luke Kenneth Casson... | add external core verilog wrapper, ironically around...
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commit | commitdiff | tree |
| 2022-02-13 |
Luke Kenneth Casson... | bugfixing for ls2 imports of uart16550
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commit | commitdiff | tree |
| 2022-02-13 |
Luke Kenneth Casson... | Revert "remove dummy trap pipeline"
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commit | commitdiff | tree |
| 2022-02-13 |
Luke Kenneth Casson... | Revert "doh"
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commit | commitdiff | tree |
| 2022-02-09 |
Luke Kenneth Casson... | add opencores uart16550 instance wrapper
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commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | fix bug in itlb_valid SRLatch set/reset, a bit weird...
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commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | whoops tlb_valids in ICache is a combinatorial-get/set
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commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | convert TLBValidArray in ICache to SRLatch
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commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | add microwatt external core build target to Makefile
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commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | use an SRLatch for cache_valids, at least it reduces...
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commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | use Memory for cache tags in dcache
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commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | use Memory for cache_tags in icache
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commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | doh
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commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | remove dummy trap pipeline
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commit | commitdiff | tree |
| 2022-01-31 |
Luke Kenneth Casson... | remove combinatorial loop from MultiCompUnit
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commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | break out cache_tags and cache_valids (again) this...
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commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | remove CacheTagArray in icache.py
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commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | create Memory for Cache Tags in I-Cache
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commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | remove unneeded parameter
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commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | add Array of CacheValids back in, so as to reduce LUT4...
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commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | tagset is a local Signal in ICache
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commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | identify combinatorial loop signals in MultiCompUnit...
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commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | use nmigen Memory in I-Cache for TLB Lookups
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commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | put itlb_valid back, ready for conversion to Memory...
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commit | commitdiff | tree |
| 2022-01-30 |
Luke Kenneth Casson... | convert CacheRAM to Memory, acts much faster now
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commit | commitdiff | tree |
| 2022-01-29 |
Luke Kenneth Casson... | explanatory comment when page hit is the same for stores
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commit | commitdiff | tree |
| 2022-01-29 |
Luke Kenneth Casson... | use right offset in dcache wb address
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commit | commitdiff | tree |
| 2022-01-29 |
Luke Kenneth Casson... | re-examining dcache.vhdl, still did not get the store...
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commit | commitdiff | tree |
| 2022-01-29 |
Luke Kenneth Casson... | bug in dcache.py where when two stores occur in the...
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commit | commitdiff | tree |
| 2022-01-28 |
Luke Kenneth Casson... | in LoadStore1 capture the address for misaligned dual...
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commit | commitdiff | tree |
| 2022-01-28 |
Luke Kenneth Casson... | sort out misaligned store in LoadStore1
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commit | commitdiff | tree |
| 2022-01-27 |
Luke Kenneth Casson... | for second aligned request truncate address to nearest...
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commit | commitdiff | tree |
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