self._ctrl_info_r = bank.csr(64, "rw") # control info
self._dram_init_r = bank.csr(64, "r") # dram initialisation info
self._spiflash_info_r = bank.csr(64, "r") # spi flash info
self._uart0_info_r = bank.csr(64, "r") # UART0 info (baud etc.)
self._uart1_info_r = bank.csr(64, "r") # UART1 info (baud etc.)
self._bram_bootaddr_r = bank.csr(64, "r") # BRAM boot address
self._ctrl_info_r = bank.csr(64, "rw") # control info
self._dram_init_r = bank.csr(64, "r") # dram initialisation info
self._spiflash_info_r = bank.csr(64, "r") # spi flash info
self._uart0_info_r = bank.csr(64, "r") # UART0 info (baud etc.)
self._uart1_info_r = bank.csr(64, "r") # UART1 info (baud etc.)
self._bram_bootaddr_r = bank.csr(64, "r") # BRAM boot address