3 # SPDX-License-Identifier: LGPLv3+
4 # Copyright (C) 2022 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 # Copyright (C) 2022 Raptor Engineering, LLC <support@raptorengineering.com>
6 # Sponsored by NLnet and NGI POINTER under EU Grants 871528 and 957073
7 # Part of the Libre-SOC Project.
9 # this is a System Console peripheral compatible with microwatt
10 # https://github.com/antonblanchard/microwatt/blob/master/syscon.vhdl
12 from nmigen
import (Elaboratable
, Cat
, Module
, Signal
)
13 from nmigen
.cli
import rtlil
, verilog
15 from lambdasoc
.periph
import Peripheral
17 __all__
= ["MicrowattSYSCON"]
20 class MicrowattSYSCON(Peripheral
, Elaboratable
):
21 """Microwatt-compatible (Sys)tem (Con)figuration module
24 def __init__(self
, *, sys_clk_freq
=100e6
,
31 super().__init
__(name
="syscon")
32 self
.sys_clk_freq
= sys_clk_freq
33 self
.core_clk_freq
= core_clk_freq
34 self
.has_uart
= has_uart
35 self
.spi_offset
= spi_offset
36 self
.dram_addr
= dram_addr
37 self
.uart_is_16550
= uart_is_16550
39 # System control ports
40 self
.dram_at_0
= Signal()
41 self
.core_reset
= Signal()
42 self
.soc_reset
= Signal()
44 # set up a CSR Bank and associated bridge. has to be in this order
45 # (declare bank, declare bridge) for some unknown reason.
46 # (r)ead regs will have a r_stb and r_data Record entry
47 # (w)rite regs will have a w_stb and w_data Record entry
48 bank
= self
.csr_bank()
49 self
._reg
_sig
_r
= bank
.csr(64, "r") # signature
50 self
._reg
_info
_r
= bank
.csr(64, "r") # info
51 self
._bram
_info
_r
= bank
.csr(64, "r") # bram info
52 self
._dram
_info
_r
= bank
.csr(64, "r") # dram info
53 self
._clk
_info
_r
= bank
.csr(64, "r") # nest clock frequency
54 self
._ctrl
_info
_r
= bank
.csr(64, "rw") # control info
55 self
._dram
_init
_r
= bank
.csr(64, "r") # dram initialisation info
56 self
._spiflash
_info
_r
= bank
.csr(64, "r") # spi flash info
57 self
._uart
0_info
_r
= bank
.csr(64, "r") # UART0 info (baud etc.)
58 self
._uart
1_info
_r
= bank
.csr(64, "r") # UART1 info (baud etc.)
59 self
._bram
_bootaddr
_r
= bank
.csr(64, "r") # BRAM boot address
60 self
._core
_clk
_info
_r
= bank
.csr(64, "r") # core clock frequency
62 # bridge the above-created CSRs over wishbone. ordering and size
63 # above mattered, the bridge automatically packs them together
64 # as memory-addressable "things" for us
65 self
._bridge
= self
.bridge(data_width
=32, granularity
=8, alignment
=3)
66 self
.bus
= self
._bridge
.bus
68 def elaborate(self
, platform
):
70 comb
, sync
= m
.d
.comb
, m
.d
.comb
71 m
.submodules
.bridge
= self
._bridge
73 # enter data into the CSRs. r_data can be left live all the time,
74 # w_data obviously has to be set only when w_stb triggers.
76 # identifying signature
77 comb
+= self
._reg
_sig
_r
.r_data
.eq(0xf00daa5500010001)
79 # nest clock rate (hz)
80 comb
+= self
._clk
_info
_r
.r_data
.eq(int(self
.sys_clk_freq
)) # in hz
82 # core clock rate (hz)
83 comb
+= self
._core
_clk
_info
_r
.r_data
.eq(int(self
.core_clk_freq
)) # in hz
86 has_spi
= self
.spi_offset
is not None
87 has_dram
= self
.dram_addr
is not None
89 # uart peripheral clock rate, currently assumed to be system clock
90 # 0 ..31 : UART clock freq (in HZ)
91 # 32 : UART is 16550 (otherwise pp)
92 comb
+= self
._uart
0_info
_r
.r_data
[0:32].eq(int(self
.sys_clk_freq
))
93 comb
+= self
._uart
0_info
_r
.r_data
[32].eq(1)
95 # Reg Info, defines what peripherals and characteristics are present
96 comb
+= self
._reg
_info
_r
.r_data
[0].eq(self
.has_uart
) # has UART0
97 comb
+= self
._reg
_info
_r
.r_data
[1].eq(has_dram
) # has DDR DRAM
98 comb
+= self
._reg
_info
_r
.r_data
[3].eq(has_spi
) # has SPI Flash
99 comb
+= self
._reg
_info
_r
.r_data
[5].eq(1) # Large SYSCON
102 sysctrl
= Cat(self
.dram_at_0
, self
.core_reset
, self
.soc_reset
)
103 with m
.If(self
._ctrl
_info
_r
.w_stb
):
104 sync
+= sysctrl
.eq(self
._ctrl
_info
_r
.w_data
)
105 comb
+= self
._ctrl
_info
_r
.r_data
.eq(sysctrl
)
108 comb
+= self
._spiflash
_info
_r
.r_data
.eq(self
.spi_offset
or 0)
113 def create_ilang(dut
, ports
, test_name
):
114 vl
= rtlil
.convert(dut
, name
=test_name
, ports
=ports
)
115 with
open("%s.il" % test_name
, "w") as f
:
118 def create_verilog(dut
, ports
, test_name
):
119 vl
= verilog
.convert(dut
, name
=test_name
, ports
=ports
)
120 with
open("%s.v" % test_name
, "w") as f
:
124 if __name__
== "__main__":
125 from nmigen_soc
import wishbone
126 class QuickDemo(Elaboratable
):
127 def elaborate(self
, platform
):
129 arbiter
= wishbone
.Arbiter(addr_width
=30, data_width
=32,
131 decoder
= wishbone
.Decoder(addr_width
=30, data_width
=32,
133 m
.submodules
.syscon
= syscon
= MicrowattSYSCON()
134 m
.submodules
.decoder
= decoder
135 m
.submodules
.arbiter
= arbiter
136 decoder
.add(syscon
.bus
, addr
=0xc0000000)
137 m
.d
.comb
+= arbiter
.bus
.connect(decoder
.bus
)
140 create_ilang(m
, None, "syscondemo")