Separate core and nest clocks in Microwatt SYSCON

diff --git a/src/soc/bus/syscon.py b/src/soc/bus/syscon.py
index b5826565cb026bd3650343477c6d66e37615dcaf..3a9de4fcb7de0c100cf8bcaaf1783e7f60461375 100644 (file)
--- a/src/soc/bus/syscon.py
+++ b/src/soc/bus/syscon.py
@@ -2,6 +2,7 @@
 #
 # SPDX-License-Identifier: LGPLv3+
 # Copyright (C) 2022 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+# Copyright (C) 2022 Raptor Engineering, LLC <support@raptorengineering.com>
 # Sponsored by NLnet and NGI POINTER under EU Grants 871528 and 957073
 # Part of the Libre-SOC Project.
 #
@@ -21,6 +22,7 @@ class MicrowattSYSCON(Peripheral, Elaboratable):
     """
 
     def __init__(self, *, sys_clk_freq=100e6,
+                          core_clk_freq=100e6,
                           spi_offset=None,
                           dram_addr=None,
                           has_uart=True,
@@ -28,6 +30,7 @@ class MicrowattSYSCON(Peripheral, Elaboratable):
                           ):
         super().__init__(name="syscon")
         self.sys_clk_freq = sys_clk_freq
+        self.core_clk_freq = core_clk_freq
         self.has_uart = has_uart
         self.spi_offset = spi_offset
         self.dram_addr = dram_addr
@@ -47,13 +50,14 @@ class MicrowattSYSCON(Peripheral, Elaboratable):
         self._reg_info_r      = bank.csr(64, "r") # info
         self._bram_info_r     = bank.csr(64, "r") # bram info
         self._dram_info_r     = bank.csr(64, "r") # dram info
-        self._clk_info_r      = bank.csr(64, "r") # clock frequency
+        self._clk_info_r      = bank.csr(64, "r") # nest clock frequency
         self._ctrl_info_r     = bank.csr(64, "rw") # control info
         self._dram_init_r     = bank.csr(64, "r") # dram initialisation info
         self._spiflash_info_r = bank.csr(64, "r") # spi flash info
         self._uart0_info_r    = bank.csr(64, "r") # UART0 info (baud etc.)
         self._uart1_info_r    = bank.csr(64, "r") # UART1 info (baud etc.)
         self._bram_bootaddr_r = bank.csr(64, "r") # BRAM boot address
+        self._core_clk_info_r = bank.csr(64, "r") # core clock frequency
 
         # bridge the above-created CSRs over wishbone.  ordering and size
         # above mattered, the bridge automatically packs them together
@@ -72,9 +76,12 @@ class MicrowattSYSCON(Peripheral, Elaboratable):
         # identifying signature
         comb += self._reg_sig_r.r_data.eq(0xf00daa5500010001)
 
-        # system clock rate (hz)
+        # nest clock rate (hz)
         comb += self._clk_info_r.r_data.eq(int(self.sys_clk_freq)) # in hz
 
+        # core clock rate (hz)
+        comb += self._core_clk_info_r.r_data.eq(int(self.core_clk_freq)) # in hz
+
         # detect peripherals
         has_spi = self.spi_offset is not None
         has_dram = self.dram_addr is not None