whoops forgot to make CU decisions based on latched opcode

diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py
index 41b73d1156cbfeba300cd4d3b43069f14e3ecc98..1735e24cf09e6fc2a273fcf139b0feed99f6e101 100644 (file)
--- a/src/experiment/compalu.py
+++ b/src/experiment/compalu.py
@@ -51,6 +51,7 @@ class ComputationUnitNoDelay(Elaboratable):
         self.go_die_i = Signal() # go die (reset)
 
         self.oper_i = Signal(opwid, reset_less=True) # opcode in
         self.go_die_i = Signal() # go die (reset)
 
         self.oper_i = Signal(opwid, reset_less=True) # opcode in

+        self.imm_i = Signal(rwid, reset_less=True) # immediate in

         self.src1_i = Signal(rwid, reset_less=True) # oper1 in
         self.src2_i = Signal(rwid, reset_less=True) # oper2 in
 
         self.src1_i = Signal(rwid, reset_less=True) # oper1 in
         self.src2_i = Signal(rwid, reset_less=True) # oper2 in
 


@@ -102,11 +103,11 @@ class ComputationUnitNoDelay(Elaboratable):
         with m.If(opc_l.qn):
             m.d.sync += self.counter.eq(0)
         with m.If(req_l.qn & busy_o & (self.counter == 0)):
         with m.If(opc_l.qn):
             m.d.sync += self.counter.eq(0)
         with m.If(req_l.qn & busy_o & (self.counter == 0)):

-            with m.If(self.oper_i == 2): # MUL, to take 5 instructions
+            with m.If(self.alu.op == 2): # MUL, to take 5 instructions

                 m.d.sync += self.counter.eq(5)
                 m.d.sync += self.counter.eq(5)

-            with m.Elif(self.oper_i == 3): # SHIFT to take 7
+            with m.Elif(self.alu.op == 3): # SHIFT to take 7

                 m.d.sync += self.counter.eq(7)
                 m.d.sync += self.counter.eq(7)

-            with m.Elif(self.oper_i >= 4): # Branches take 6 (to test shadow)
+            with m.Elif(self.alu.op >= 4): # Branches take 6 (to test shadow)

                 m.d.sync += self.counter.eq(6)
             with m.Else(): # ADD/SUB to take 2
                 m.d.sync += self.counter.eq(2)
                 m.d.sync += self.counter.eq(6)
             with m.Else(): # ADD/SUB to take 2
                 m.d.sync += self.counter.eq(2)

diff --git a/src/experiment/compldst.py b/src/experiment/compldst.py
index 15aebee0fe0ff2f6c27f74f116e0e7b71dc6004d..f67d75b0a822c2cf19c24645f1cca7d3c1aa03bd 100644 (file)
--- a/src/experiment/compldst.py
+++ b/src/experiment/compldst.py
@@ -172,12 +172,7 @@ class LDSTCompUnit(Elaboratable):
         with m.If(opc_l.qn):
             sync += self.counter.eq(0) # reset counter when not busy
         with m.If(req_l.qn & busy_o & (self.counter == 0)):
         with m.If(opc_l.qn):
             sync += self.counter.eq(0) # reset counter when not busy
         with m.If(req_l.qn & busy_o & (self.counter == 0)):

-            with m.If(self.oper_i == 2): # MUL, to take 5 instructions
-                sync += self.counter.eq(5)
-            with m.Elif(self.oper_i == 3): # SHIFT to take 7
-                sync += self.counter.eq(7)
-            with m.Else(): # ADD/SUB to take 2
-                sync += self.counter.eq(2)
+            sync += self.counter.eq(2) # take 2 (fake) cycles to respond

         with m.If(self.counter > 1):
             sync += self.counter.eq(self.counter - 1)
         with m.If(self.counter == 1):
         with m.If(self.counter > 1):
             sync += self.counter.eq(self.counter - 1)
         with m.If(self.counter == 1):