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Merge branch 'master' of https://git.libre-riscv.org/git/soc
[soc.git] / src / regfile /
2019-06-18 Luke Kenneth Casso... add address and output mode from LDSTCUs tree | commitdiff
2019-05-15 Luke Kenneth Casso... very weird: invert readable vector, cscore works tree | commitdiff
2019-05-14 Luke Kenneth Casso... experimenting with cscore, overlapping instructions tree | commitdiff
2019-05-08 Luke Kenneth Casso... disable writethru for now tree | commitdiff
2019-05-08 Luke Kenneth Casso... add regfile array test tree | commitdiff
2019-05-08 Luke Kenneth Casso... start on unit test tree | commitdiff
2019-05-08 Luke Kenneth Casso... whoops connect enable / data correct way round in regfi... tree | commitdiff
2019-05-08 Luke Kenneth Casso... add ORing of port inputs together tree | commitdiff
2019-05-08 Luke Kenneth Casso... add names to read/write ports, add priority picker... tree | commitdiff
2019-05-07 Luke Kenneth Casso... add a variant of a regfile that has individual read... tree | commitdiff
2019-05-07 Luke Kenneth Casso... add regfile.py tree | commitdiff