wire assignments
authorTobias Platen <tplaten@posteo.de>
Fri, 24 Jan 2020 08:54:03 +0000 (09:54 +0100)
committerTobias Platen <tplaten@posteo.de>
Fri, 24 Jan 2020 08:54:03 +0000 (09:54 +0100)
absyn.py
examples/assignment2.sv [new file with mode: 0644]
parse_sv.py

index ba356d5..a199daa 100644 (file)
--- a/absyn.py
+++ b/absyn.py
@@ -50,6 +50,7 @@ class Absyn:
         self.outputfile = None
         self.assign = []
         self.ports = []
+        self.wires = []
 
     def open(self):
         if(self.outputfile is None):
@@ -83,6 +84,12 @@ class Absyn:
         self.ports += [port]
         return port
 
+    def isPort(self, name):
+        for p in self.ports:
+            if(str(p.name) == str(name)):
+                return True
+        return False
+
     def initFunc(self, ports, params):
         params = [Leaf(token.LPAR, '('), Leaf(
             token.NAME, "self")] + [Leaf(token.RPAR, ')')]
@@ -116,12 +123,27 @@ class Absyn:
         stmts.children.append(Leaf(token.STRING, "m = Module()"))
         stmts.children.append(self.nl())
 
+        for w in self.wires:
+            wirename = w[0]
+            hasdims = (len(w) >= 4)
+            stmts.children.append(self.indent(2))
+            stmts.children.append(Leaf(token.STRING, wirename))
+            stmts.children.append(Leaf(token.STRING, " = Signal("))
+            if(hasdims):
+                stmts.children.append(Leaf(token.STRING, str(w[3])))
+            stmts.children.append(Leaf(token.STRING, ")"))
+            stmts.children.append(self.nl())
+
         for a in self.assign:
             stmts.children.append(self.indent(2))
             # m.d.sync += self.left.eq(right)
-            stmts.children.append(Leaf(token.STRING, "m.d.comb += self."))
+            stmts.children.append(Leaf(token.STRING, "m.d.comb += "))
+            if(self.isPort(a.left)):
+                stmts.children.append(Leaf(token.STRING, "self."))
             stmts.children.append(Leaf(token.STRING, a.left))
-            stmts.children.append(Leaf(token.STRING, ".eq(self."))
+            stmts.children.append(Leaf(token.STRING, ".eq("))
+            if(self.isPort(a.right)):
+                stmts.children.append(Leaf(token.STRING, "self."))
             stmts.children.append(Leaf(token.STRING, a.right))
             stmts.children.append(Leaf(token.STRING, ")"))
             stmts.children.append(self.nl())
@@ -162,6 +184,14 @@ class Absyn:
         self.printpy(str(clsdecl))
         return clsdecl
 
+    def module_item_2(self, signaltype, dims, mlist):
+        if(signaltype == "wire"):
+            for m in mlist:
+                if(dims):
+                    self.wires.append(m+dims)
+                else:
+                    self.wires.append(m)
+
     def appendComments(self, data):
         self.open()
         self.outputfile.write(data)
diff --git a/examples/assignment2.sv b/examples/assignment2.sv
new file mode 100644 (file)
index 0000000..22e0ab4
--- /dev/null
@@ -0,0 +1,9 @@
+module assignment(
+    output o,
+    input i
+);
+wire x,y;
+wire [15:0] z;
+assign x = i;
+assign o = x;
+endmodule
index 08c2925..c1c0a9c 100644 (file)
@@ -1035,6 +1035,7 @@ def p_data_type_or_implicit_3(p):
     '''data_type_or_implicit : dimensions '''
     if(parse_debug):
         print('data_type_or_implicit_3', list(p))
+    p[0] = list(p)
 
     # { vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, false, p[1]);
     #  tmp->implicit_flag = true;
@@ -8046,8 +8047,9 @@ def p_module_item_2(p):
     '''module_item : attribute_list_opt net_type data_type_or_implicit delay3_opt net_variable_list ';' '''
     if(parse_debug):
         print('module_item_2', list(p))
-        
-    p[0] = ["module_item_2"]+list(p)
+
+    p[0] = absyn.module_item_2(p[2], p[3], p[5])
+    #p[0] = ["module_item_2"]+list(p)
 
     # { data_type_t*data_type = p[3];
     #  if (data_type == 0) {
@@ -9174,10 +9176,12 @@ def p_bit_logic_opt_2(p):
 
 def p_net_type_1(p):
     '''net_type : K_wire '''
-    if(parse_debug>2):
+    if(parse_debug > 2):
         print('net_type_1', list(p))
 
     p[0] = "wire"
+
+
 ()
 
 
@@ -10083,25 +10087,27 @@ def p_register_variable_list_2(p):
 
 def p_net_variable_1(p):
     '''net_variable : IDENTIFIER dimensions_opt '''
-    if(parse_debug>2):
+    if(parse_debug > 2):
         print('net_variable_1', list(p))
-        
-    p[0]= ('net_variable_1', list(p))
-        
+
+    #p[0]= ('net_variable_1', list(p))
+
     # { perm_string name = lex_strings.make(p[1]);
     #  pform_makewire(@1, name, NetNet::IMPLICIT,
     #                 NetNet::NOT_A_PORT, IVL_VT_NO_TYPE, 0);
     #  pform_set_reg_idx(name, p[2]);
-    #p[0] = [p[1],p[2]]
+    p[0] = [p[1], p[2]]
+
+
     #       }
 ()
 
 
 def p_net_variable_list_1(p):
     '''net_variable_list : net_variable '''
-    if(parse_debug>2):
+    if(parse_debug > 2):
         print('net_variable_list_1', list(p))
-    p[0] = ('net_variable_list_1', list(p))
+    p[0] = [p[1]]
 
     # { list<perm_string>*tmp = new list<perm_string>;
     #            tmp->push_back(lex_strings.make(p[1]));
@@ -10113,9 +10119,9 @@ def p_net_variable_list_1(p):
 
 def p_net_variable_list_2(p):
     '''net_variable_list : net_variable_list ',' net_variable '''
-    if(parse_debug>2):
+    if(parse_debug > 2):
         print('net_variable_list_2', list(p))
-    p[0] = ('net_variable_list_2', list(p))
+    p[0] = p[1]+[p[3]]
 
     # { list<perm_string>*tmp = p[1];
     #            tmp->push_back(lex_strings.make(p[3]));