Partially revert GIT hash 180026c72f0e1d3ef365b2214288d4a543a238dd
[gram.git] / gram / phy / ecp5ddrphy.py
2022-04-07 Raptor Engineering... Partially revert GIT hash 180026c72f0e1d3ef365b2214288d...
2022-04-07 Raptor Engineering... Properly connect reset and cs signals
2022-03-17 Luke Kenneth Casso... initialise bitslip with a specific value rather than...
2022-03-11 Luke Kenneth Casso... annoyingly reverting reset_n naming back to reset
2022-03-10 Luke Kenneth Casso... tidyup on gramWishbone class, add comments
2022-02-26 Luke Kenneth Casso... use dict for lookup of DFI to pads names
2022-02-25 Luke Kenneth Casso... get chipselect (cs_n) name right in ECP5DDRPHY
2022-02-25 Luke Kenneth Casso... set name of DFI interface to ecp5phy in ECP5DDRPHY
2022-02-25 Luke Kenneth Casso... allow DDR3 reset (rst) signal to be controlled by DFI...
2022-02-22 Luke Kenneth Casso... remove continue/skip and add comment that all
2022-02-16 Luke Kenneth Casso... fix ECP5DDRPHY cs declaration
2020-08-07 Jean THOMASgram.phy.ecp5ddrphy: Fix ECP5DDRPHYInit (wrong domains)
2020-08-07 Jean THOMASgram.phy.ecp5ddrphy: Remove internal signal for delay
2020-08-07 Jean THOMASgram.phy.ecp5ddrphy: Detect burstdet on rising edge...
2020-08-06 Jean THOMASgram.phy.ecp5ddrphy: Make non-critical signals reset...
2020-08-06 Jean THOMASgram.phy.ecp5ddrphy: Revert to LiteDRAM's dqs_re
2020-08-06 Jean THOMASgram.phy.ecp5ddrphy: Remove unused stream import
2020-08-06 Jean THOMASgram.phy.ecp5ddrphy: Add documentation for _DQSBUFMSett...
2020-08-06 Jean THOMASgram.phy.ecp5ddrphy: Fix DQSBUFM's pause signal (fixes...
2020-08-06 Jean THOMASgram.phy.ecp5ddrphy: Code cleaning
2020-08-04 Jean THOMASRaise ValueError if the number of DQ pads is not a...
2020-08-04 Jean THOMASSample data based on datavalid signal (fixes #47)
2020-08-04 Jean THOMASMake burstdet_reg reset-less
2020-08-03 Jean THOMASRevert to dqs_re from LiteDRAM
2020-08-03 Jean THOMASUse DiffPairs for DQS
2020-07-29 Jean THOMASRemove datavalid signal
2020-07-28 Jean THOMASStop feeding DQSBUFM with constant 1 on its READx inputs
2020-07-28 Jean THOMASSimplify tck expression
2020-07-27 Jean THOMASUse If instead of a Switch
2020-07-27 Jean THOMASFix wrong T1 signal
2020-07-27 Jean THOMASAdd comment
2020-07-23 Jean THOMASRevert to timings from LiteDRAM
2020-07-23 Jean THOMASFix code styling
2020-07-23 Jean THOMASFix burstdet CSR code
2020-07-22 Jean THOMASRemove unnecessary signal reset
2020-07-22 Jean THOMASRework burstdet CSR code
2020-07-21 Jean THOMASRework CSR interface for PHY
2020-07-21 Jean THOMASFix write timings
2020-07-21 Jean THOMASReplace Switch with If statement, indentation fixup
2020-07-20 Jean THOMASApply changes from LiteDRAM#fa7d91a
2020-07-20 Jean THOMASFix code styling
2020-07-20 Jean THOMASRemove useless signal
2020-07-20 Jean THOMASUse PinsN when possible (fixes #27)
2020-07-20 Jean THOMASSimplify PHY read code
2020-07-17 Jean THOMASUse XDR for RAS#, CAS#, WE#, CLK_EN and ODT
2020-07-17 Jean THOMASCode cleaning in ECP5 PHY
2020-07-17 Jean THOMASUse XDR for ba pins
2020-07-17 Jean THOMASUse XDR for address pins
2020-07-17 Jean THOMASFix when there are multiple clocks
2020-07-17 Jean THOMASUse nMigen's XDR for DDR clk
2020-07-17 Jean THOMASRemove unused signal
2020-07-17 Jean THOMASFix code styling
2020-07-17 Jean THOMASUse the right domain
2020-07-17 Jean THOMASFix PHY issues
2020-07-17 Jean THOMASRemove event in ECP5DDRPHY
2020-07-17 Jean THOMASRemove comment
2020-07-07 Jean THOMASReplace cke with clk_en
2020-07-03 Jean THOMASRemove remainings from TRELLIS_IO
2020-07-02 Jean THOMASUse reset signal from dramsync instead of sync
2020-06-30 Jean THOMASApplying #9044c10 changes in LiteDRAM (phy/ecp5ddrphy...
2020-06-29 Jean THOMASFix DQSBUFM floating DYNDELAY
2020-06-29 Jean THOMASUse BB instead of TRELLIS_IO
2020-06-22 Jean THOMASUse TRELLIS_IO instead of BB in ECP5 PHY
2020-06-18 Jean THOMASUse BB instance for bidirectionnal IOs
2020-06-17 Jean THOMASRollback PHY changes, use raw pins
2020-06-16 Jean THOMASPartially fix the tristate IOs on DDR3 RAM
2020-06-16 Jean THOMASFix oMigen cases and resource syntax
2020-06-16 Jean THOMASFix old CSRStatus code
2020-06-16 Jean THOMASFix variable read as an attribute
2020-06-16 Jean THOMASUpdate switch to nMigen syntax
2020-06-16 Jean THOMASFix CSR attribute error
2020-06-16 Jean THOMASFix CSR attribute error
2020-06-16 Jean THOMASFix pin count error (related to #9)
2020-06-16 Jean THOMASFix pin count error (related to #9)
2020-06-12 Jean THOMASFix clock signal for ECP5 PHY
2020-06-11 Jean THOMASRename sys2x to sync2x
2020-06-10 Jean THOMASAdd self._bridge to m.submodules (fixing #4)
2020-06-09 Jean THOMASRun autopep8
2020-06-08 Jean THOMASFix bugs in ECP5DDRPHY instanciation
2020-06-08 Jean THOMASRework DFI interface code
2020-06-04 Jean THOMASCorrect nMigen transition bugs
2020-06-04 Jean THOMASMore nMigen conversion and fixes
2020-06-03 Jean THOMASInitial commit