match up PLL names
[libresoc-litex.git] / ls180soc.py
2021-05-22 Luke Kenneth Casso... match up PLL names
2021-04-18 Luke Kenneth Casso... rename PLL pins to match LIP6.fr PLL
2021-04-18 Luke Kenneth Casso... rename XICS memmap regions
2021-04-18 Luke Kenneth Casso... update to build ls180 4k SRAMs
2021-04-05 Luke Kenneth Casso... sort out sdr and sdmmc OE pad drive, no longer one...
2021-04-01 Luke Kenneth Casso... disable PLL for litex build, new variant
2021-03-29 Luke Kenneth Casso... must not add bus width parameter
2021-03-28 Luke Kenneth Casso... fix issues with port direction on several pads
2021-03-27 Luke Kenneth Casso... latest fighting with litex to get pad directions connec...
2021-03-25 Luke Kenneth Casso... debugging ls180 litex hell
2021-03-22 Luke Kenneth Casso... SDR pad mask output for DM
2021-03-12 Luke Kenneth Casso... splitting out litex files from soc repo into separate...