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Remove unused GHDL_TARGET_GENERICS
2021-03-25 Anton BlanchardRemove unused GHDL_TARGET_GENERICS
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2021-03-25 Anton BlanchardMove verilator --trace flag into VERILATOR_FLAGS
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2021-03-24 Anton BlanchardRemove -frelaxed
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2021-03-24 Anton BlanchardUse VERILATOR_FLAGS/VERILATOR_CFLAGS on all verilator...
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2021-03-24 Anton BlanchardRemove core_files from soc_files and fpga_files
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2021-03-15 Anton BlanchardAllow SPI BOOT_CLOCKS to be overridden by top level
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2021-03-15 Anton BlanchardPass icache/dcache/tlb parameters down from soc
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2021-02-08 Anton BlanchardAdd some wishbone checking
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2021-01-03 Anton BlanchardInitialize PID register
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2021-01-03 Anton BlanchardFix another reset issue in spi_rxtx
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2021-01-03 Anton BlanchardReset cmd_ready_o in spi_txrx
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2021-01-03 Anton BlanchardReset TB and DECR
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2020-12-20 Anton BlanchardMake wishbone_master_out and wb_io_master_out match
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2020-12-15 Anton BlanchardReset JTAG/DMI
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2020-12-14 Anton BlanchardFix an issue in flash controller when BOOT_CLOCKS is...
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2020-12-13 Anton BlanchardFully initialize FPU buses when FPU is disabled
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2020-12-12 Anton BlanchardFix a few reset issues in flash controller
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2020-12-08 Anton BlanchardAdd LOG_LENGTH to top-generic.vhdl
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2020-12-07 Anton BlanchardAdd verilator FPGA target
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2020-12-07 Anton BlanchardFix verilator build
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2020-12-06 Anton BlanchardFix ghdl warning due to variable shadowing in icache
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2020-12-03 Anton BlanchardReduce hello_world footprint to fit in 8kB
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2020-05-23 Anton BlanchardPass clock frequency to UART sim wrapper
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2020-05-20 Anton BlanchardA little less shouting in the Makefile
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2020-05-20 Anton BlanchardFix the simulated DMI
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2020-05-20 Anton BlanchardExit cleanly from testbench on success
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2020-05-20 Anton BlanchardMerge Makefile and Makefile.synth
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2020-05-20 Anton BlanchardAdd Makefile command line variables to enable docker...
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2020-05-20 Anton BlanchardRework Makefile
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2020-05-19 Anton BlanchardImprove make clean
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2020-05-19 Anton BlanchardAdd yosys/verilator support
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2020-05-19 Anton BlanchardFix yosys build after MMU merge
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2020-05-19 Anton BlanchardSome yosys fixes
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2020-04-16 Anton Blanchardrust_lib_demo: Remove bin2hex.py
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2020-04-16 Anton Blanchardhello_world: Use Makefile automatic variables
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2020-04-16 Anton Blanchardrust_lib_demo: Use common console code
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2020-04-16 Anton Blanchardrust_lib_demo: Update package dependencies to fix a...
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2020-04-16 Tom VijlbriefAdd Rust demo
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2020-01-23 Anton BlanchardFix a Diamond issue in decode2
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2020-01-23 Anton BlanchardFix a Diamond build issue in writeback
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2020-01-22 Anton BlanchardConsolidate VHPI code
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2020-01-22 Anton Blanchardsim_console: Use cfmakeraw() and add option for ctrl...
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2020-01-21 Anton BlanchardUpdate Makefile.synth after Paul's patches
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2020-01-21 Anton BlanchardAdd some information about GHDL backend issues
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2020-01-21 Anton BlanchardAdd an option to use Docker
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2020-01-21 Anton BlanchardInitial support for ghdl synthesis
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2020-01-21 Anton BlanchardFix Makefile dependency issue with files in vhdl/*
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2020-01-20 Anton BlanchardImprove dependencies.py and add a --synth option
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2020-01-19 Anton BlanchardAdd a few FFs on the RX input to avoid metastability...
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2020-01-19 Anton BlanchardReduce simulated and default FPGA RAM to 384kB
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2020-01-19 Anton BlanchardAdd log2ceil and use it in bram code
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2020-01-19 Anton BlanchardUpdate micropython
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2020-01-19 Anton Blanchardhello_world updates
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2020-01-11 Anton BlanchardMove bin2hex.py to scripts/
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2020-01-11 Anton BlanchardFix a ghdlsynth issue in fast_spr_num
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2020-01-11 Anton BlanchardFix a ghdlsynth issue in icache
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2020-01-11 Anton BlanchardRemoved unused core_terminated signal
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2020-01-11 Anton BlanchardFix some ghdlsynth issues with fpga_bram
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2020-01-11 Anton BlanchardFix ghdlsynth issue in register file
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2020-01-11 Anton BlanchardRemove unused signal
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2020-01-11 Anton BlanchardFix a ghdysynth inferred latch error in writeback
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2020-01-11 Anton BlanchardFix a ghdysynth inferred latch error in execute
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2020-01-11 Anton BlanchardUpper 32 bits of XER should read as 0s
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2020-01-11 Anton BlanchardDump CTR, LR and CR on sim termination, and update...
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2020-01-10 Anton BlanchardPoint to upstream micropython
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2019-12-11 Anton Blanchardcontrol: Fix build issue with Fedora 31 version of...
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2019-12-09 Anton BlanchardAdd SPI configuration to Xilinx constraint files
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2019-10-17 Anton Blanchardisel takes a CR bit, not a CR field
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2019-10-15 Anton BlanchardAdd CR hazard detection
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2019-10-14 Anton BlanchardRemove issue restrictions on a number of instructions
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2019-10-14 Anton BlanchardAdd GPR hazard detection
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2019-10-14 Anton BlanchardSeparate issue control into its own unit
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2019-10-13 Anton Blanchardmod* doesn't have an RC form
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2019-10-13 Anton BlanchardFix clk_gen_bypass
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2019-10-13 Anton Blancharddecode: Handle icbi
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2019-10-13 Anton Blanchardfifo: Reformat
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2019-10-13 Anton Blanchardfifo: Remove shared variable
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2019-10-11 Anton BlanchardDon't infer latch for newcrf
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2019-10-10 Anton BlanchardFix cmod-a7 frequency
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2019-10-10 Anton BlanchardLimit outstanding range
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2019-10-10 Anton BlanchardFix count-leading/trailing-zeroes
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2019-10-08 Anton BlanchardConsolidate logical instructions
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2019-09-24 Anton BlanchardRemove gcc software divide patch
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2019-09-24 Anton BlanchardFix build issue in dmi_dtm_dummy.vhdl
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2019-09-24 Anton BlanchardUpdate Makefile dependencies
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2019-09-24 Anton BlanchardMerge branch 'divider' of https://github.com/paulusmack...
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2019-09-24 Anton BlanchardRename OP_SUBFC -> OP_SUBFE, OP_ADDC -> OP_ADDE
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2019-09-23 Anton BlanchardTerminate test on illegal instruction
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2019-09-23 Anton BlanchardFix ghdl error
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2019-09-23 Anton BlanchardAdd core_debug.vhdl to fusesoc configs
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2019-09-19 Anton BlanchardReformat crhelpers, and remove some stale code
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2019-09-19 Anton BlanchardReformat helpers
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2019-09-19 Anton BlanchardReformat insn_helpers
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2019-09-19 Anton BlanchardReformat loadstore1
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2019-09-19 Anton BlanchardReformat loadstore2
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2019-09-19 Anton Blanchardloads don't do both byte reversal and sign extension
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2019-09-19 Anton BlanchardReformat wishbone code
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2019-09-19 Anton BlanchardReformat glibc_random
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2019-09-19 Anton BlanchardReformat simple_ram_behavioural
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2019-09-19 Anton BlanchardReformat sim_console
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