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2022-04-15	Luke Kenneth Casson...	add features option to gramCore and PHY wishbone buses...	commit \| commitdiff \| tree
2022-04-15	Luke Kenneth Casson...	fix reset to be xdr=4x in ECP5DDRPHY	commit \| commitdiff \| tree
2022-04-15	Luke Kenneth Casson...	connect (new) reset signal on IOPads which comes from...	commit \| commitdiff \| tree
2022-04-14	Luke Kenneth Casson...	whilst IOpads and PLLs were driving from dramsync,...	commit \| commitdiff \| tree
2022-03-17	Luke Kenneth Casson...	initialise bitslip with a specific value rather than...	commit \| commitdiff \| tree
2022-03-17	Luke Kenneth Casson...	add alternative variant of runsimsoc.sh	commit \| commitdiff \| tree
2022-03-13	Luke Kenneth Casson...	add 1024M_ddr3_parameters.vh for MT41K64M16	commit \| commitdiff \| tree
2022-03-11	Luke Kenneth Casson...	add a 2nd clock, this one deliberately the	commit \| commitdiff \| tree
2022-03-11	Luke Kenneth Casson...	annoyingly reverting reset_n naming back to reset	commit \| commitdiff \| tree
2022-03-10	Luke Kenneth Casson...	tidyup on gramWishbone class, add comments	commit \| commitdiff \| tree
2022-03-10	Luke Kenneth Casson...	tidy up gramWishbone constructor, pass Wishbone features...	commit \| commitdiff \| tree
2022-03-10	Luke Kenneth Casson...	code-cleanup and copyright notices	commit \| commitdiff \| tree
2022-03-01	Luke Kenneth Casson...	fix up simulation to be more like VERSA_ECP5	commit \| commitdiff \| tree
2022-02-28	Luke Kenneth Casson...	remove unneeded import	commit \| commitdiff \| tree
2022-02-26	Luke Kenneth Casson...	use dict for lookup of DFI to pads names	commit \| commitdiff \| tree
2022-02-26	Luke Kenneth Casson...	add missing reset-HI values to cas_n, cs_n, we_n and...	commit \| commitdiff \| tree
2022-02-25	Luke Kenneth Casson...	get chipselect (cs_n) name right in ECP5DDRPHY	commit \| commitdiff \| tree
2022-02-25	Luke Kenneth Casson...	restore naming convention "cs_r" on DFI Interface	commit \| commitdiff \| tree
2022-02-25	Luke Kenneth Casson...	set name of DFI interface to ecp5phy in ECP5DDRPHY	commit \| commitdiff \| tree
2022-02-25	Luke Kenneth Casson...	allow DDR3 reset (rst) signal to be controlled by DFI...	commit \| commitdiff \| tree
2022-02-24	Luke Kenneth Casson...	add a BitSlip module	commit \| commitdiff \| tree
2022-02-24	Luke Kenneth Casson...	replace the simulation Clock-Reset-Generator with one...	commit \| commitdiff \| tree
2022-02-24	Luke Kenneth Casson...	add CSRs to FakePHY which allows at least testing of...	commit \| commitdiff \| tree
2022-02-22	Luke Kenneth Casson...	remove continue/skip and add comment that all	commit \| commitdiff \| tree
2022-02-21	Luke Kenneth Casson...	add debug print statements to investigate FakePHY	commit \| commitdiff \| tree
2022-02-21	Luke Kenneth Casson...	add a debug verilog dump of one of the FakePHY SocTest...	commit \| commitdiff \| tree
2022-02-20	Luke Kenneth Casson...	add dfii submodules so they get explicit names	commit \| commitdiff \| tree
2022-02-20	Luke Kenneth Casson...	add name to DFI Interface (helps gtkwave traces)	commit \| commitdiff \| tree
2022-02-19	Luke Kenneth Casson...	fix gram unit test imports	commit \| commitdiff \| tree
2022-02-16	Luke Kenneth Casson...	fix ECP5DDRPHY cs declaration	commit \| commitdiff \| tree

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