setup.py: Removed deps as per bug #1086#c7.
[gram.git] / examples /
2022-07-23 Cesar StraussRemove unused Minerva CPU import from headless examples
2022-04-10 Raptor Engineering... Don't reset the core / peripherals on DRAM controller...
2022-04-10 Raptor Engineering... Put sysclk2x back under system reset control
2022-04-09 Raptor Engineering... Revert "Avoid timing violation on ECP5 PHY PAUSE signal"
2022-04-09 Raptor Engineering... Avoid timing violation on ECP5 PHY PAUSE signal
2022-04-09 Raptor Engineering... Wire up missing CRG / DDR3 clock control / reset signals
2022-04-07 Raptor Engineering... Working at 50MHz system clock
2022-04-07 Raptor Engineering... Switch CRG back over to ECP5 version
2022-04-07 Raptor Engineering... Properly connect reset and cs signals
2022-04-07 Raptor Engineering... Add initial support for external DRAM init on the Rapto...
2020-08-07 Jean THOMASexamples: Display rdly map
2020-08-06 Jean THOMASexamples: Load stock calibration profile if calibration...
2020-08-06 Jean THOMASexamples: Make frequency a parameter
2020-08-06 Jean THOMASexamples: Continue self-test even if calibration is...
2020-08-03 Jean THOMASUse mainstream ECPIX5 platform file (fixing #38)
2020-08-03 Jean THOMASFix memtest abort
2020-08-03 Jean THOMASAdd auto calibration result check, abort memtest if...
2020-08-03 Jean THOMASRemove we_n from xdr list
2020-08-03 Jean THOMASUse DiffPairs for DQS
2020-08-03 Jean THOMASRemove comment
2020-08-03 Jean THOMASRemove we_n in xdr list
2020-07-30 Jean THOMASAdd rdly auto calibration
2020-07-30 Jean THOMASAdd burstdet code
2020-07-30 Jean THOMASRemove unnecessary volatile qualifier
2020-07-30 Jean THOMASFix identation
2020-07-30 Jean THOMASRemove write logging and change loop conditions
2020-07-30 Jean THOMASFix identation
2020-07-30 Jean THOMASRemove hardcoded MRx, use gramProfile instead
2020-07-30 Jean THOMASRemove main.img.bin target, add clean target
2020-07-29 Jean THOMASFix peripheral addresses, improve memory testing
2020-07-29 Jean THOMASAdd example SoC code
2020-07-24 Jean THOMASAdd memtest score
2020-07-23 Jean THOMASParametric test size, add delay option between write...
2020-07-23 Jean THOMASUse clk pin definition from upstream nmigen-boards
2020-07-22 Jean THOMASHandle rdly customization
2020-07-22 Jean THOMASFix granularity and sel in UARTBridge
2020-07-22 Jean THOMASFix ECPIX585Platform to work with the latest commits...
2020-07-21 Jean THOMASRemove commented DDR3 resource definition
2020-07-20 Jean THOMASSet SEL when reading
2020-07-20 Jean THOMASUse PinsN when possible (fixes #27)
2020-07-17 Jean THOMASUse XDR for ba pins
2020-07-17 Jean THOMASUse XDR for address pins
2020-07-17 Jean THOMASUse nMigen's XDR for DDR clk
2020-07-17 Jean THOMASFix CRG parameters
2020-07-15 Jean THOMASRemove arbiter from headless-ecpix5 example
2020-07-15 Jean THOMASUse random values for memtest
2020-07-13 Jean THOMASPer bytes error highlighting
2020-07-10 Jean THOMASRemove unused files
2020-07-10 Jean THOMASPut every gram component in the dramsync clock domain
2020-07-10 Jean THOMASUse clock freq from platform
2020-07-10 Jean THOMASUse R02 platform file
2020-07-10 Jean THOMASExternalize CRG
2020-07-10 Jean THOMASFix DDR3 module parameter
2020-07-10 Jean THOMASRework headless client interface
2020-07-09 Jean THOMASMake power-on delay signal synchronous
2020-07-09 Jean THOMASFix formatting in headless example
2020-07-08 Jean THOMASUpdate memtest code
2020-07-07 Jean THOMASFix CRG PLL parameters (fixing #23)
2020-07-03 Jean THOMASUse CRG parameters that actually work on hardware
2020-06-25 Jean THOMASSet UART bridge SEL signals to 0xF
2020-06-22 Jean THOMASRollback to the ECP5 P/N used in ECPIX-5
2020-06-22 Jean THOMASFix pinout
2020-06-17 Jean THOMASRemove lambdasoc dependency from UARTBridge
2020-06-16 Jean THOMASAdd example code for headless SoC
2020-06-12 Jean THOMASAdd while(1) loop to firmware
2020-06-11 Jean THOMASRename sys2x to sync2x
2020-06-11 Jean THOMASFix comparison value
2020-06-11 Jean THOMASMake memory test code more verbose
2020-06-10 Jean THOMASAdd test firmware
2020-06-10 Jean THOMASFix missing submodule statement in ECPIX5 example
2020-06-09 Jean THOMASAutopep8 on example code
2020-06-09 Jean THOMASRework LiteDRAM wishbone frontend (wip)
2020-06-08 Jean THOMASConnect dramcore to SoC bus in ECPIX-5 example
2020-06-08 Jean THOMASFix PLL
2020-06-04 Jean THOMASAdd dram core as submodule
2020-06-04 Jean THOMASAdd second clock
2020-06-04 Jean THOMASRemove diff pairs in ECPIX5Platform
2020-06-03 Jean THOMASInitial commit