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rv64[ms]i-csr: Only emit F instructions when compiled for F.
author
Richard Xia
<rxia@sifive.com>
Mon, 7 Aug 2017 23:57:14 +0000
(16:57 -0700)
committer
Richard Xia
<rxia@sifive.com>
Mon, 7 Aug 2017 23:57:14 +0000
(16:57 -0700)
isa/rv64si/csr.S
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diff --git
a/isa/rv64si/csr.S
b/isa/rv64si/csr.S
index 0576678d47171ea86b654a05d658f9f4ee1df719..83e9cae243ae80a9a2bea06d36f545ceb1b306aa 100644
(file)
--- a/
isa/rv64si/csr.S
+++ b/
isa/rv64si/csr.S
@@
-47,10
+47,15
@@
RVTEST_CODE_BEGIN
# If so, make sure FP stores have no effect when mstatus.FS is off.
li a1, MSTATUS_FS
csrs mstatus, a1
# If so, make sure FP stores have no effect when mstatus.FS is off.
li a1, MSTATUS_FS
csrs mstatus, a1
+#ifdef __riscv_flen
fmv.s.x f0, x0
csrc mstatus, a1
la a1, fsw_data
TEST_CASE(10, a0, 1, fsw f0, (a1); lw a0, (a1));
fmv.s.x f0, x0
csrc mstatus, a1
la a1, fsw_data
TEST_CASE(10, a0, 1, fsw f0, (a1); lw a0, (a1));
+#else
+ # Fail if this test is compiled without F but executed on a core with F.
+ TEST_CASE(10, zero, 1)
+#endif
1:
# Figure out if 'U' is set in misa
1:
# Figure out if 'U' is set in misa
@@
-58,7
+63,7
@@
RVTEST_CODE_BEGIN
srli a0, a0, 20 # a0 = a0 >> 20
andi a0, a0, 1 # a0 = a0 & 1
beqz a0, finish # if no user mode, skip the rest of these checks
srli a0, a0, 20 # a0 = a0 >> 20
andi a0, a0, 1 # a0 = a0 & 1
beqz a0, finish # if no user mode, skip the rest of these checks
-#endif
+#endif
/* __MACHINE_MODE */
# jump to user land
li t0, SSTATUS_SPP
# jump to user land
li t0, SSTATUS_SPP