xilinx mig: track changes in rocket-chip

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
index b52b37c0e699b99b2e1c453bb9f37e927582100f..4586949c0eada15181f58e5c4186f7118fa87841 100644 (file)
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
@@ -11,7 +11,7 @@ trait PeripheryXilinxVC707MIG extends TopNetwork {
 
   val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
   require(p(BankedL2Config).nMemoryChannels == 1, "Coreplex must have 1 master memory port")
-  val mem = Seq(xilinxvc707mig.node)
+  xilinxvc707mig.node := mem(0).node
 }
 
 trait PeripheryXilinxVC707MIGBundle extends TopNetworkBundle {