cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 from migen import *
  30 from migen.fhdl import verilog
  31 from migen.fhdl.structure import _Operator
  32
  33 from riscvdefs import *
  34 from cpudefs import *
  35
  36 class MemoryInterface:
  37     fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
  38     fetch_data = Signal(32, name="memory_interface_fetch_data")
  39     fetch_valid = Signal(name="memory_interface_fetch_valid")
  40     rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
  41     rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
  42     rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
  43     rw_active = Signal(name="memory_interface_rw_active")
  44     rw_data_in = Signal(32, name="memory_interface_rw_data_in")
  45     rw_data_out = Signal(32, name="memory_interface_rw_data_out")
  46     rw_address_valid = Signal(name="memory_interface_rw_address_valid")
  47     rw_wait = Signal(name="memory_interface_rw_wait")
  48
  49
  50 class CPU(Module):
  51     """
  52     """
  53
  54     def get_ls_misaligned(self, ls, funct3, load_store_address_low_2):
  55         return Case(funct3[:2],
  56                 { F3.sb: ls.eq(Constant(0)),
  57                   F3.sh: ls.eq(load_store_address_low_2[0] != 0),
  58                   F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)),
  59                   "default": ls.eq(Constant(1))
  60                 })
  61
  62     def get_lsbm(self, decoder_funct3):
  63         return Cat(Constant(1),
  64                    Mux((decoder_funct3[1] | decoder_funct3[0]),
  65                        Constant(1), Constant(0)),
  66                    Mux((decoder_funct3[1]),
  67                        Constant(0b11, 2), Constant(0, 2)))
  68
  69     def __init__(self):
  70         #self.clk = ClockSignal()
  71         #self.reset = ResetSignal()
  72         self.tty_write = Signal()
  73         self.tty_write_data = Signal(8)
  74         self.tty_write_busy = Signal()
  75         self.switch_2 = Signal()
  76         self.switch_3 = Signal()
  77         self.led_1 = Signal()
  78         self.led_3 = Signal()
  79
  80         ram_size = Constant(0x8000)
  81         ram_start = Constant(0x10000, 32)
  82         reset_vector = Signal(32)
  83         mtvec = Signal(32)
  84
  85         reset_vector.eq(ram_start)
  86         mtvec.eq(ram_start + 0x40)
  87
  88         l = []
  89         for i in range(31):
  90             l.append(Signal(32, name="register%d" % i))
  91         registers = Array(l)
  92
  93         mi = MemoryInterface()
  94
  95         mii = Instance("cpu_memory_interface", name="memory_instance",
  96                     p_ram_size = ram_size,
  97                     p_ram_start = ram_start,
  98                     i_clk=ClockSignal(),
  99                     i_rst=ResetSignal(),
 100                     i_fetch_address = mi.fetch_address,
 101                     o_fetch_data = mi.fetch_data,
 102                     o_fetch_valid = mi.fetch_valid,
 103                     i_rw_address = mi.rw_address,
 104                     i_rw_byte_mask = mi.rw_byte_mask,
 105                     i_rw_read_not_write = mi.rw_read_not_write,
 106                     i_rw_active = mi.rw_active,
 107                     i_rw_data_in = mi.rw_data_in,
 108                     o_rw_data_out = mi.rw_data_out,
 109                     o_rw_address_valid = mi.rw_address_valid,
 110                     o_rw_wait = mi.rw_wait,
 111                     o_tty_write = self.tty_write,
 112                     o_tty_write_data = self.tty_write_data,
 113                     i_tty_write_busy = self.tty_write_busy,
 114                     i_switch_2 = self.switch_2,
 115                     i_switch_3 = self.switch_3,
 116                     o_led_1 = self.led_1,
 117                     o_led_3 = self.led_3
 118                   )
 119         self.specials += mii
 120
 121         fetch_act = Signal(fetch_action)
 122         fetch_target_pc = Signal(32)
 123         fetch_output_pc = Signal(32)
 124         fetch_output_instruction = Signal(32)
 125         fetch_output_st = Signal(fetch_output_state)
 126
 127         fs = Instance("CPUFetchStage", name="fetch_stage",
 128             i_clk=ClockSignal(),
 129             i_rst=ResetSignal(),
 130             o_memory_interface_fetch_address = mi.fetch_address,
 131             i_memory_interface_fetch_data = mi.fetch_data,
 132             i_memory_interface_fetch_valid = mi.fetch_valid,
 133             i_fetch_action = fetch_act,
 134             i_target_pc = fetch_target_pc,
 135             o_output_pc = fetch_output_pc,
 136             o_output_instruction = fetch_output_instruction,
 137             o_output_state = fetch_output_st,
 138             i_reset_vector = reset_vector,
 139             i_mtvec = mtvec,
 140         )
 141         self.specials += fs
 142
 143         decoder_funct7 = Signal(7)
 144         decoder_funct3 = Signal(3)
 145         decoder_rd = Signal(5)
 146         decoder_rs1 = Signal(5)
 147         decoder_rs2 = Signal(5)
 148         decoder_immediate = Signal(32)
 149         decoder_opcode = Signal(7)
 150         decode_act = Signal(decode_action)
 151
 152         cd = Instance("CPUDecoder", name="decoder",
 153             i_instruction = fetch_output_instruction,
 154             o_funct7 = decoder_funct7,
 155             o_funct3 = decoder_funct3,
 156             o_rd = decoder_rd,
 157             o_rs1 = decoder_rs1,
 158             o_rs2 = decoder_rs2,
 159             o_immediate = decoder_immediate,
 160             o_opcode = decoder_opcode,
 161             o_decode_action = decode_act
 162         )
 163         self.specials += cd
 164
 165         register_rs1 = Signal(32)
 166         register_rs2 = Signal(32)
 167         self.comb += If(decoder_rs1 == 0,
 168                         register_rs1.eq(0)
 169                      ).Else(
 170                         register_rs1.eq(registers[decoder_rs1-1]))
 171         self.comb += If(decoder_rs2 == 0,
 172                         register_rs2.eq(0)
 173                      ).Else(
 174                         register_rs2.eq(registers[decoder_rs2-1]))
 175
 176         load_store_address = Signal(32)
 177         load_store_address_low_2 = Signal(2)
 178
 179         self.comb += load_store_address.eq(decoder_immediate + register_rs1)
 180         self.comb += load_store_address_low_2.eq(
 181                             decoder_immediate[:2] + register_rs1[:2])
 182
 183         load_store_misaligned = Signal()
 184
 185         lsa = self.get_ls_misaligned(load_store_misaligned, decoder_funct3,
 186                                      load_store_address_low_2)
 187         self.comb += lsa
 188
 189         # XXX rwaddr not 31:2 any more
 190         self.comb += mi.rw_address.eq(load_store_address[2:])
 191
 192         unshifted_load_store_byte_mask = Signal(4)
 193
 194         self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(
 195                                                        decoder_funct3))
 196
 197         # XXX yuck.  this will cause migen simulation to fail
 198         # (however conversion to verilog works)
 199         self.comb += mi.rw_byte_mask.eq(
 200                 _Operator("<<", [unshifted_load_store_byte_mask,
 201                                         load_store_address_low_2]))
 202
 203         # XXX not obvious
 204         b3 = Mux(load_store_address_low_2[1],
 205                  Mux(load_store_address_low_2[0], register_rs2[0:8],
 206                                                   register_rs2[8:16]),
 207                  Mux(load_store_address_low_2[0], register_rs2[16:24],
 208                                                   register_rs2[24:32]))
 209         b2 = Mux(load_store_address_low_2[1], register_rs2[0:8],
 210                                               register_rs2[16:24])
 211         b1 = Mux(load_store_address_low_2[0], register_rs2[0:8],
 212                                               register_rs2[8:16])
 213         b0 = register_rs2[0:8]
 214
 215         self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
 216
 217         # XXX not obvious
 218         unmasked_loaded_value = Signal(32)
 219
 220         b0 = Mux(load_store_address_low_2[1],
 221                  Mux(load_store_address_low_2[0], mi.rw_data_out[24:32],
 222                                                   mi.rw_data_out[16:24]),
 223                  Mux(load_store_address_low_2[0], mi.rw_data_out[15:8],
 224                                                   mi.rw_data_out[0:8]))
 225         b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31],
 226                                               mi.rw_data_out[8:16])
 227         b23 = mi.rw_data_out[16:32]
 228
 229         self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
 230
 231         # XXX not obvious
 232         loaded_value = Signal(32)
 233
 234         b0 = unmasked_loaded_value[0:8]
 235         b1 = Mux(decoder_funct3[0:2] == 0,
 236                 Replicate(~decoder_funct3[2] & unmasked_loaded_value[7], 8),
 237                 unmasked_loaded_value[8:16])
 238         b2 = Mux(decoder_funct3[1] == 0,
 239                 Replicate(~decoder_funct3[2] &
 240                            Mux(decoder_funct3[0], unmasked_loaded_value[15],
 241                                                   unmasked_loaded_value[7]),
 242                           16),
 243                 unmasked_loaded_value[16:32])
 244
 245         self.comb += loaded_value.eq(Cat(b0, b1, b2))
 246
 247 if __name__ == "__main__":
 248     example = CPU()
 249     print(verilog.convert(example,
 250          {
 251            example.tty_write,
 252            example.tty_write_data,
 253            example.tty_write_busy,
 254            example.switch_2,
 255            example.switch_3,
 256            example.led_1,
 257            example.led_3,
 258            }))
 259
 260 """
 261
 262     assign memory_interface_rw_active = ~reset
 263                                         & (fetch_output_state == `fetch_output_state_valid)
 264                                         & ~load_store_misaligned
 265                                         & ((decode_action & (`decode_action_load | `decode_action_store)) != 0);
 266
 267     assign memory_interface_rw_read_not_write = ~decoder_opcode[5];
 268
 269     wire [31:0] alu_a = register_rs1;
 270     wire [31:0] alu_b = decoder_opcode[5] ? register_rs2 : decoder_immediate;
 271     wire [31:0] alu_result;
 272
 273     cpu_alu alu(
 274         .funct7(decoder_funct7),
 275         .funct3(decoder_funct3),
 276         .opcode(decoder_opcode),
 277         .a(alu_a),
 278         .b(alu_b),
 279         .result(alu_result)
 280         );
 281
 282     wire [31:0] lui_auipc_result = decoder_opcode[5] ? decoder_immediate : decoder_immediate + fetch_output_pc;
 283
 284     assign fetch_target_pc[31:1] = ((decoder_opcode != `opcode_jalr ? fetch_output_pc[31:1] : register_rs1[31:1]) + decoder_immediate[31:1]);
 285     assign fetch_target_pc[0] = 0;
 286
 287     wire misaligned_jump_target = fetch_target_pc[1];
 288
 289     wire [31:0] branch_arg_a = {register_rs1[31] ^ ~decoder_funct3[1], register_rs1[30:0]};
 290     wire [31:0] branch_arg_b = {register_rs2[31] ^ ~decoder_funct3[1], register_rs2[30:0]};
 291
 292     wire branch_taken = decoder_funct3[0] ^ (decoder_funct3[2] ? branch_arg_a < branch_arg_b : branch_arg_a == branch_arg_b);
 293
 294     reg [31:0] mcause = 0;
 295     reg [31:0] mepc = 32'hXXXXXXXX;
 296     reg [31:0] mscratch = 32'hXXXXXXXX;
 297
 298     reg mstatus_mpie = 1'bX;
 299     reg mstatus_mie = 0;
 300     parameter mstatus_mprv = 0;
 301     parameter mstatus_tsr = 0;
 302     parameter mstatus_tw = 0;
 303     parameter mstatus_tvm = 0;
 304     parameter mstatus_mxr = 0;
 305     parameter mstatus_sum = 0;
 306     parameter mstatus_xs = 0;
 307     parameter mstatus_fs = 0;
 308     parameter mstatus_mpp = 2'b11;
 309     parameter mstatus_spp = 0;
 310     parameter mstatus_spie = 0;
 311     parameter mstatus_upie = 0;
 312     parameter mstatus_sie = 0;
 313     parameter mstatus_uie = 0;
 314
 315     reg mie_meie = 1'bX;
 316     reg mie_mtie = 1'bX;
 317     reg mie_msie = 1'bX;
 318     parameter mie_seie = 0;
 319     parameter mie_ueie = 0;
 320     parameter mie_stie = 0;
 321     parameter mie_utie = 0;
 322     parameter mie_ssie = 0;
 323     parameter mie_usie = 0;
 324
 325     task reset_to_initial;
 326     begin
 327         mcause = 0;
 328         mepc = 32'hXXXXXXXX;
 329         mscratch = 32'hXXXXXXXX;
 330         mstatus_mie = 0;
 331         mstatus_mpie = 1'bX;
 332         mie_meie = 1'bX;
 333         mie_mtie = 1'bX;
 334         mie_msie = 1'bX;
 335         registers['h01] <= 32'hXXXXXXXX;
 336         registers['h02] <= 32'hXXXXXXXX;
 337         registers['h03] <= 32'hXXXXXXXX;
 338         registers['h04] <= 32'hXXXXXXXX;
 339         registers['h05] <= 32'hXXXXXXXX;
 340         registers['h06] <= 32'hXXXXXXXX;
 341         registers['h07] <= 32'hXXXXXXXX;
 342         registers['h08] <= 32'hXXXXXXXX;
 343         registers['h09] <= 32'hXXXXXXXX;
 344         registers['h0A] <= 32'hXXXXXXXX;
 345         registers['h0B] <= 32'hXXXXXXXX;
 346         registers['h0C] <= 32'hXXXXXXXX;
 347         registers['h0D] <= 32'hXXXXXXXX;
 348         registers['h0E] <= 32'hXXXXXXXX;
 349         registers['h0F] <= 32'hXXXXXXXX;
 350         registers['h10] <= 32'hXXXXXXXX;
 351         registers['h11] <= 32'hXXXXXXXX;
 352         registers['h12] <= 32'hXXXXXXXX;
 353         registers['h13] <= 32'hXXXXXXXX;
 354         registers['h14] <= 32'hXXXXXXXX;
 355         registers['h15] <= 32'hXXXXXXXX;
 356         registers['h16] <= 32'hXXXXXXXX;
 357         registers['h17] <= 32'hXXXXXXXX;
 358         registers['h18] <= 32'hXXXXXXXX;
 359         registers['h19] <= 32'hXXXXXXXX;
 360         registers['h1A] <= 32'hXXXXXXXX;
 361         registers['h1B] <= 32'hXXXXXXXX;
 362         registers['h1C] <= 32'hXXXXXXXX;
 363         registers['h1D] <= 32'hXXXXXXXX;
 364         registers['h1E] <= 32'hXXXXXXXX;
 365         registers['h1F] <= 32'hXXXXXXXX;
 366     end
 367     endtask
 368
 369     task write_register(input [4:0] register_number, input [31:0] value);
 370     begin
 371         if(register_number != 0)
 372             registers[register_number] <= value;
 373     end
 374     endtask
 375
 376     function [31:0] evaluate_csr_funct3_operation(input [2:0] funct3, input [31:0] previous_value, input [31:0] written_value);
 377     begin
 378         case(funct3)
 379         `funct3_csrrw, `funct3_csrrwi:
 380             evaluate_csr_funct3_operation = written_value;
 381         `funct3_csrrs, `funct3_csrrsi:
 382             evaluate_csr_funct3_operation = written_value | previous_value;
 383         `funct3_csrrc, `funct3_csrrci:
 384             evaluate_csr_funct3_operation = ~written_value & previous_value;
 385         default:
 386             evaluate_csr_funct3_operation = 32'hXXXXXXXX;
 387         endcase
 388     end
 389     endfunction
 390
 391     parameter misa_a = 1'b0;
 392     parameter misa_b = 1'b0;
 393     parameter misa_c = 1'b0;
 394     parameter misa_d = 1'b0;
 395     parameter misa_e = 1'b0;
 396     parameter misa_f = 1'b0;
 397     parameter misa_g = 1'b0;
 398     parameter misa_h = 1'b0;
 399     parameter misa_i = 1'b1;
 400     parameter misa_j = 1'b0;
 401     parameter misa_k = 1'b0;
 402     parameter misa_l = 1'b0;
 403     parameter misa_m = 1'b0;
 404     parameter misa_n = 1'b0;
 405     parameter misa_o = 1'b0;
 406     parameter misa_p = 1'b0;
 407     parameter misa_q = 1'b0;
 408     parameter misa_r = 1'b0;
 409     parameter misa_s = 1'b0;
 410     parameter misa_t = 1'b0;
 411     parameter misa_u = 1'b0;
 412     parameter misa_v = 1'b0;
 413     parameter misa_w = 1'b0;
 414     parameter misa_x = 1'b0;
 415     parameter misa_y = 1'b0;
 416     parameter misa_z = 1'b0;
 417     parameter misa = {
 418         2'b01,
 419         4'b0,
 420         misa_z,
 421         misa_y,
 422         misa_x,
 423         misa_w,
 424         misa_v,
 425         misa_u,
 426         misa_t,
 427         misa_s,
 428         misa_r,
 429         misa_q,
 430         misa_p,
 431         misa_o,
 432         misa_n,
 433         misa_m,
 434         misa_l,
 435         misa_k,
 436         misa_j,
 437         misa_i,
 438         misa_h,
 439         misa_g,
 440         misa_f,
 441         misa_e,
 442         misa_d,
 443         misa_c,
 444         misa_b,
 445         misa_a};
 446
 447     parameter mvendorid = 32'b0;
 448     parameter marchid = 32'b0;
 449     parameter mimpid = 32'b0;
 450     parameter mhartid = 32'b0;
 451
 452     function [31:0] make_mstatus(input mstatus_tsr,
 453         input mstatus_tw,
 454         input mstatus_tvm,
 455         input mstatus_mxr,
 456         input mstatus_sum,
 457         input mstatus_mprv,
 458         input [1:0] mstatus_xs,
 459         input [1:0] mstatus_fs,
 460         input [1:0] mstatus_mpp,
 461         input mstatus_spp,
 462         input mstatus_mpie,
 463         input mstatus_spie,
 464         input mstatus_upie,
 465         input mstatus_mie,
 466         input mstatus_sie,
 467         input mstatus_uie);
 468     begin
 469         make_mstatus = {(mstatus_xs == 2'b11) | (mstatus_fs == 2'b11),
 470             8'b0,
 471             mstatus_tsr,
 472             mstatus_tw,
 473             mstatus_tvm,
 474             mstatus_mxr,
 475             mstatus_sum,
 476             mstatus_mprv,
 477             mstatus_xs,
 478             mstatus_fs,
 479             mstatus_mpp,
 480             2'b0,
 481             mstatus_spp,
 482             mstatus_mpie,
 483             1'b0,
 484             mstatus_spie,
 485             mstatus_upie,
 486             mstatus_mie,
 487             1'b0,
 488             mstatus_sie,
 489             mstatus_uie};
 490     end
 491     endfunction
 492
 493     wire mip_meip = 0; // TODO: implement external interrupts
 494     parameter mip_seip = 0;
 495     parameter mip_ueip = 0;
 496     wire mip_mtip = 0; // TODO: implement timer interrupts
 497     parameter mip_stip = 0;
 498     parameter mip_utip = 0;
 499     parameter mip_msip = 0;
 500     parameter mip_ssip = 0;
 501     parameter mip_usip = 0;
 502
 503     wire csr_op_is_valid;
 504
 505     function `fetch_action get_fetch_action(
 506         input `fetch_output_state fetch_output_state,
 507         input `decode_action decode_action,
 508         input load_store_misaligned,
 509         input memory_interface_rw_address_valid,
 510         input memory_interface_rw_wait,
 511         input branch_taken,
 512         input misaligned_jump_target,
 513         input csr_op_is_valid
 514         );
 515     begin
 516         case(fetch_output_state)
 517         `fetch_output_state_empty:
 518             get_fetch_action = `fetch_action_default;
 519         `fetch_output_state_trap:
 520             get_fetch_action = `fetch_action_ack_trap;
 521         `fetch_output_state_valid: begin
 522             if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 523                 get_fetch_action = `fetch_action_error_trap;
 524             end
 525             else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 526                 get_fetch_action = `fetch_action_noerror_trap;
 527             end
 528             else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
 529                 if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
 530                     get_fetch_action = `fetch_action_error_trap;
 531                 end
 532                 else if(memory_interface_rw_wait) begin
 533                     get_fetch_action = `fetch_action_wait;
 534                 end
 535                 else begin
 536                     get_fetch_action = `fetch_action_default;
 537                 end
 538             end
 539             else if((decode_action & `decode_action_fence_i) != 0) begin
 540                 get_fetch_action = `fetch_action_fence;
 541             end
 542             else if((decode_action & `decode_action_branch) != 0) begin
 543                 if(branch_taken) begin
 544                     if(misaligned_jump_target) begin
 545                         get_fetch_action = `fetch_action_error_trap;
 546                     end
 547                     else begin
 548                         get_fetch_action = `fetch_action_jump;
 549                     end
 550                 end
 551                 else
 552                 begin
 553                     get_fetch_action = `fetch_action_default;
 554                 end
 555             end
 556             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 557                 if(misaligned_jump_target) begin
 558                     get_fetch_action = `fetch_action_error_trap;
 559                 end
 560                 else begin
 561                     get_fetch_action = `fetch_action_jump;
 562                 end
 563             end
 564             else if((decode_action & `decode_action_csr) != 0) begin
 565                 if(csr_op_is_valid)
 566                     get_fetch_action = `fetch_action_default;
 567                 else
 568                     get_fetch_action = `fetch_action_error_trap;
 569             end
 570             else begin
 571                 get_fetch_action = `fetch_action_default;
 572             end
 573         end
 574         default:
 575             get_fetch_action = 32'hXXXXXXXX;
 576         endcase
 577     end
 578     endfunction
 579
 580     assign fetch_action = get_fetch_action(
 581         fetch_output_state,
 582         decode_action,
 583         load_store_misaligned,
 584         memory_interface_rw_address_valid,
 585         memory_interface_rw_wait,
 586         branch_taken,
 587         misaligned_jump_target,
 588         csr_op_is_valid
 589         );
 590
 591     task handle_trap;
 592     begin
 593         mstatus_mpie = mstatus_mie;
 594         mstatus_mie = 0;
 595         mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
 596         if(fetch_action == `fetch_action_ack_trap) begin
 597             mcause = `cause_instruction_access_fault;
 598         end
 599         else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 600             mcause = `cause_illegal_instruction;
 601         end
 602         else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 603             mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
 604         end
 605         else if((decode_action & `decode_action_load) != 0) begin
 606             if(load_store_misaligned)
 607                 mcause = `cause_load_address_misaligned;
 608             else
 609                 mcause = `cause_load_access_fault;
 610         end
 611         else if((decode_action & `decode_action_store) != 0) begin
 612             if(load_store_misaligned)
 613                 mcause = `cause_store_amo_address_misaligned;
 614             else
 615                 mcause = `cause_store_amo_access_fault;
 616         end
 617         else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
 618             mcause = `cause_instruction_address_misaligned;
 619         end
 620         else begin
 621             mcause = `cause_illegal_instruction;
 622         end
 623     end
 624     endtask
 625
 626     wire [11:0] csr_number = decoder_immediate;
 627     wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
 628     wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
 629     wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
 630
 631     function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
 632     begin
 633         case(csr_number)
 634         `csr_ustatus,
 635         `csr_fflags,
 636         `csr_frm,
 637         `csr_fcsr,
 638         `csr_uie,
 639         `csr_utvec,
 640         `csr_uscratch,
 641         `csr_uepc,
 642         `csr_ucause,
 643         `csr_utval,
 644         `csr_uip,
 645         `csr_sstatus,
 646         `csr_sedeleg,
 647         `csr_sideleg,
 648         `csr_sie,
 649         `csr_stvec,
 650         `csr_scounteren,
 651         `csr_sscratch,
 652         `csr_sepc,
 653         `csr_scause,
 654         `csr_stval,
 655         `csr_sip,
 656         `csr_satp,
 657         `csr_medeleg,
 658         `csr_mideleg,
 659         `csr_dcsr,
 660         `csr_dpc,
 661         `csr_dscratch:
 662             get_csr_op_is_valid = 0;
 663         `csr_cycle,
 664         `csr_time,
 665         `csr_instret,
 666         `csr_cycleh,
 667         `csr_timeh,
 668         `csr_instreth,
 669         `csr_mvendorid,
 670         `csr_marchid,
 671         `csr_mimpid,
 672         `csr_mhartid:
 673             get_csr_op_is_valid = ~csr_writes;
 674         `csr_misa,
 675         `csr_mstatus,
 676         `csr_mie,
 677         `csr_mtvec,
 678         `csr_mscratch,
 679         `csr_mepc,
 680         `csr_mcause,
 681         `csr_mip:
 682             get_csr_op_is_valid = 1;
 683         `csr_mcounteren,
 684         `csr_mtval,
 685         `csr_mcycle,
 686         `csr_minstret,
 687         `csr_mcycleh,
 688         `csr_minstreth:
 689             // TODO: CSRs not implemented yet
 690             get_csr_op_is_valid = 0;
 691         endcase
 692     end
 693     endfunction
 694
 695     assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
 696
 697     wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
 698     wire [63:0] time_counter = 0; // TODO: implement time_counter
 699     wire [63:0] instret_counter = 0; // TODO: implement instret_counter
 700
 701     always @(posedge clk) begin:main_block
 702         if(reset) begin
 703             reset_to_initial();
 704             disable main_block;
 705         end
 706         case(fetch_output_state)
 707         `fetch_output_state_empty: begin
 708         end
 709         `fetch_output_state_trap: begin
 710             handle_trap();
 711         end
 712         `fetch_output_state_valid: begin:valid
 713             if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
 714                 handle_trap();
 715             end
 716             else if((decode_action & `decode_action_load) != 0) begin
 717                 if(~memory_interface_rw_wait)
 718                     write_register(decoder_rd, loaded_value);
 719             end
 720             else if((decode_action & `decode_action_op_op_imm) != 0) begin
 721                 write_register(decoder_rd, alu_result);
 722             end
 723             else if((decode_action & `decode_action_lui_auipc) != 0) begin
 724                 write_register(decoder_rd, lui_auipc_result);
 725             end
 726             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 727                 write_register(decoder_rd, fetch_output_pc + 4);
 728             end
 729             else if((decode_action & `decode_action_csr) != 0) begin:csr
 730                 reg [31:0] csr_output_value;
 731                 reg [31:0] csr_written_value;
 732                 csr_output_value = 32'hXXXXXXXX;
 733                 csr_written_value = 32'hXXXXXXXX;
 734                 case(csr_number)
 735                 `csr_cycle: begin
 736                     csr_output_value = cycle_counter[31:0];
 737                 end
 738                 `csr_time: begin
 739                     csr_output_value = time_counter[31:0];
 740                 end
 741                 `csr_instret: begin
 742                     csr_output_value = instret_counter[31:0];
 743                 end
 744                 `csr_cycleh: begin
 745                     csr_output_value = cycle_counter[63:32];
 746                 end
 747                 `csr_timeh: begin
 748                     csr_output_value = time_counter[63:32];
 749                 end
 750                 `csr_instreth: begin
 751                     csr_output_value = instret_counter[63:32];
 752                 end
 753                 `csr_mvendorid: begin
 754                     csr_output_value = mvendorid;
 755                 end
 756                 `csr_marchid: begin
 757                     csr_output_value = marchid;
 758                 end
 759                 `csr_mimpid: begin
 760                     csr_output_value = mimpid;
 761                 end
 762                 `csr_mhartid: begin
 763                     csr_output_value = mhartid;
 764                 end
 765                 `csr_misa: begin
 766                     csr_output_value = misa;
 767                 end
 768                 `csr_mstatus: begin
 769                     csr_output_value = make_mstatus(mstatus_tsr,
 770                                                     mstatus_tw,
 771                                                     mstatus_tvm,
 772                                                     mstatus_mxr,
 773                                                     mstatus_sum,
 774                                                     mstatus_mprv,
 775                                                     mstatus_xs,
 776                                                     mstatus_fs,
 777                                                     mstatus_mpp,
 778                                                     mstatus_spp,
 779                                                     mstatus_mpie,
 780                                                     mstatus_spie,
 781                                                     mstatus_upie,
 782                                                     mstatus_mie,
 783                                                     mstatus_sie,
 784                                                     mstatus_uie);
 785                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 786                     if(csr_writes) begin
 787                         mstatus_mpie = csr_written_value[7];
 788                         mstatus_mie = csr_written_value[3];
 789                     end
 790                 end
 791                 `csr_mie: begin
 792                     csr_output_value = 0;
 793                     csr_output_value[11] = mie_meie;
 794                     csr_output_value[9] = mie_seie;
 795                     csr_output_value[8] = mie_ueie;
 796                     csr_output_value[7] = mie_mtie;
 797                     csr_output_value[5] = mie_stie;
 798                     csr_output_value[4] = mie_utie;
 799                     csr_output_value[3] = mie_msie;
 800                     csr_output_value[1] = mie_ssie;
 801                     csr_output_value[0] = mie_usie;
 802                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 803                     if(csr_writes) begin
 804                         mie_meie = csr_written_value[11];
 805                         mie_mtie = csr_written_value[7];
 806                         mie_msie = csr_written_value[3];
 807                     end
 808                 end
 809                 `csr_mtvec: begin
 810                     csr_output_value = mtvec;
 811                 end
 812                 `csr_mscratch: begin
 813                     csr_output_value = mscratch;
 814                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 815                     if(csr_writes)
 816                         mscratch = csr_written_value;
 817                 end
 818                 `csr_mepc: begin
 819                     csr_output_value = mepc;
 820                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 821                     if(csr_writes)
 822                         mepc = csr_written_value;
 823                 end
 824                 `csr_mcause: begin
 825                     csr_output_value = mcause;
 826                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 827                     if(csr_writes)
 828                         mcause = csr_written_value;
 829                 end
 830                 `csr_mip: begin
 831                     csr_output_value = 0;
 832                     csr_output_value[11] = mip_meip;
 833                     csr_output_value[9] = mip_seip;
 834                     csr_output_value[8] = mip_ueip;
 835                     csr_output_value[7] = mip_mtip;
 836                     csr_output_value[5] = mip_stip;
 837                     csr_output_value[4] = mip_utip;
 838                     csr_output_value[3] = mip_msip;
 839                     csr_output_value[1] = mip_ssip;
 840                     csr_output_value[0] = mip_usip;
 841                 end
 842                 endcase
 843                 if(csr_reads)
 844                     write_register(decoder_rd, csr_output_value);
 845             end
 846             else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin
 847                 // do nothing
 848             end
 849         end
 850         endcase
 851     end
 852
 853 endmodule
 854 """
 855