cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 import string
  30 from migen import *
  31 from migen.fhdl import verilog
  32 from migen.fhdl.structure import _Operator
  33
  34 from riscvdefs import *
  35 from cpudefs import *
  36
  37 class MemoryInterface:
  38     fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
  39     fetch_data = Signal(32, name="memory_interface_fetch_data")
  40     fetch_valid = Signal(name="memory_interface_fetch_valid")
  41     rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
  42     rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
  43     rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
  44     rw_active = Signal(name="memory_interface_rw_active")
  45     rw_data_in = Signal(32, name="memory_interface_rw_data_in")
  46     rw_data_out = Signal(32, name="memory_interface_rw_data_out")
  47     rw_address_valid = Signal(name="memory_interface_rw_address_valid")
  48     rw_wait = Signal(name="memory_interface_rw_wait")
  49
  50
  51 class Decoder:
  52     funct7 = Signal(7, name="decoder_funct7")
  53     funct3 = Signal(3, name="decoder_funct3")
  54     rd = Signal(5, name="decoder_rd")
  55     rs1 = Signal(5, name="decoder_rs1")
  56     rs2 = Signal(5, name="decoder_rs2")
  57     immediate = Signal(32, name="decoder_immediate")
  58     opcode = Signal(7, name="decoder_opcode")
  59     act = Signal(decode_action, name="decoder_action")
  60
  61 class MStatus:
  62     def __init__(self, comb, sync):
  63         self.comb = comb
  64         self.sync = sync
  65         self.mpie = Signal(name="mstatus_mpie")
  66         self.mie = Signal(name="mstatus_mie")
  67         self.mprv = Signal(name="mstatus_mprv")
  68         self.tsr = Signal(name="mstatus_tsr")
  69         self.tw = Signal(name="mstatus_tw")
  70         self.tvm = Signal(name="mstatus_tvm")
  71         self.mxr = Signal(name="mstatus_mxr")
  72         self._sum = Signal(name="mstatus_sum")
  73         self.xs = Signal(name="mstatus_xs")
  74         self.fs = Signal(name="mstatus_fs")
  75         self.mpp = Signal(2, name="mstatus_mpp")
  76         self.spp = Signal(name="mstatus_spp")
  77         self.spie = Signal(name="mstatus_spie")
  78         self.upie = Signal(name="mstatus_upie")
  79         self.sie = Signal(name="mstatus_sie")
  80         self.uie = Signal(name="mstatus_uie")
  81
  82         for n in dir(self):
  83             if n in ['mpp', 'comb', 'sync'] or n.startswith("_"):
  84                 continue
  85             self.comb += getattr(self, n).eq(0x0)
  86         self.comb += self.mpp.eq(0b11)
  87
  88         self.sync += self.mie.eq(0)
  89         self.sync += self.mpie.eq(0)
  90
  91 class MIE:
  92     def __init__(self, comb, sync):
  93         self.comb = comb
  94         self.sync = sync
  95         self.meie = Signal(name="mie_meie")
  96         self.mtie = Signal(name="mie_mtie")
  97         self.msie = Signal(name="mie_msie")
  98         self.ueie = Signal(name="mie_ueie")
  99         self.stie = Signal(name="mie_stie")
 100         self.utie = Signal(name="mie_utie")
 101         self.ssie = Signal(name="mie_ssie")
 102         self.usie = Signal(name="mie_usie")
 103
 104         for n in dir(self):
 105             if n in ['comb', 'sync'] or n.startswith("_"):
 106                 continue
 107             self.comb += getattr(self, n).eq(0x0)
 108
 109         self.sync += self.meie.eq(0)
 110         self.sync += self.mtie.eq(0)
 111         self.sync += self.msie.eq(0)
 112
 113
 114 class M:
 115     def __init__(self, comb, sync):
 116         self.comb = comb
 117         self.sync = sync
 118         self.mcause = Signal(32)
 119         self.mepc = Signal(32)
 120         self.mscratch = Signal(32)
 121         self.sync += self.mcause.eq(0)
 122         self.sync += self.mepc.eq(0) # 32'hXXXXXXXX;
 123         self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX;
 124
 125 class Misa:
 126
 127     def __init__(self, comb, sync):
 128         self.comb = comb
 129         self.sync = sync
 130         self.misa = Signal(32)
 131         cl = []
 132         for l in list(string.ascii_lowercase):
 133             value = 1 if l == 'i' else 0
 134             cl.append(Constant(value))
 135         cl.append(Constant(0, 4))
 136         cl.append(Constant(0b01, 2))
 137         self.comb += self.misa.eq(Cat(cl))
 138
 139
 140 class CPU(Module):
 141     """
 142     """
 143
 144     def get_ls_misaligned(self, ls, funct3, load_store_address_low_2):
 145         return Case(funct3[:2],
 146                 { F3.sb: ls.eq(Constant(0)),
 147                   F3.sh: ls.eq(load_store_address_low_2[0] != 0),
 148                   F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)),
 149                   "default": ls.eq(Constant(1))
 150                 })
 151
 152     def get_lsbm(self, dc):
 153         return Cat(Constant(1),
 154                    Mux((dc.funct3[1] | dc.funct3[0]),
 155                        Constant(1), Constant(0)),
 156                    Mux((dc.funct3[1]),
 157                        Constant(0b11, 2), Constant(0, 2)))
 158
 159     # XXX this happens to get done by various self.sync actions
 160     #def reset_to_initial(self, m, mstatus, mie, registers):
 161     #    return [m.mcause.eq(0),
 162     #            ]
 163
 164     def write_register(self, register_number, value):
 165         return If(register_number != 0,
 166                   self.registers[register_number].eq(value)
 167                )
 168
 169     def evaluate_csr_funct3_op(self, funct3, previous_value, written_value):
 170         c = { "default": Constant(0, 32)}
 171         for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value
 172         for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value
 173         for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value
 174         return Case(funct3, c)
 175
 176     def __init__(self):
 177         self.clk = ClockSignal()
 178         self.reset = ResetSignal()
 179         self.tty_write = Signal()
 180         self.tty_write_data = Signal(8)
 181         self.tty_write_busy = Signal()
 182         self.switch_2 = Signal()
 183         self.switch_3 = Signal()
 184         self.led_1 = Signal()
 185         self.led_3 = Signal()
 186
 187         ram_size = Constant(0x8000)
 188         ram_start = Constant(0x10000, 32)
 189         reset_vector = Signal(32)
 190         mtvec = Signal(32)
 191
 192         reset_vector.eq(ram_start)
 193         mtvec.eq(ram_start + 0x40)
 194
 195         l = []
 196         for i in range(31):
 197             r = Signal(32, name="register%d" % i)
 198             l.append(r)
 199             self.sync += r.eq(Constant(0, 32))
 200         self.registers = Array(l)
 201
 202         mi = MemoryInterface()
 203
 204         mii = Instance("cpu_memory_interface", name="memory_instance",
 205                     p_ram_size = ram_size,
 206                     p_ram_start = ram_start,
 207                     i_clk=ClockSignal(),
 208                     i_rst=ResetSignal(),
 209                     i_fetch_address = mi.fetch_address,
 210                     o_fetch_data = mi.fetch_data,
 211                     o_fetch_valid = mi.fetch_valid,
 212                     i_rw_address = mi.rw_address,
 213                     i_rw_byte_mask = mi.rw_byte_mask,
 214                     i_rw_read_not_write = mi.rw_read_not_write,
 215                     i_rw_active = mi.rw_active,
 216                     i_rw_data_in = mi.rw_data_in,
 217                     o_rw_data_out = mi.rw_data_out,
 218                     o_rw_address_valid = mi.rw_address_valid,
 219                     o_rw_wait = mi.rw_wait,
 220                     o_tty_write = self.tty_write,
 221                     o_tty_write_data = self.tty_write_data,
 222                     i_tty_write_busy = self.tty_write_busy,
 223                     i_switch_2 = self.switch_2,
 224                     i_switch_3 = self.switch_3,
 225                     o_led_1 = self.led_1,
 226                     o_led_3 = self.led_3
 227                   )
 228         self.specials += mii
 229
 230         fetch_act = Signal(fetch_action)
 231         fetch_target_pc = Signal(32)
 232         fetch_output_pc = Signal(32)
 233         fetch_output_instruction = Signal(32)
 234         fetch_output_st = Signal(fetch_output_state)
 235
 236         fs = Instance("CPUFetchStage", name="fetch_stage",
 237             i_clk=ClockSignal(),
 238             i_rst=ResetSignal(),
 239             o_memory_interface_fetch_address = mi.fetch_address,
 240             i_memory_interface_fetch_data = mi.fetch_data,
 241             i_memory_interface_fetch_valid = mi.fetch_valid,
 242             i_fetch_action = fetch_act,
 243             i_target_pc = fetch_target_pc,
 244             o_output_pc = fetch_output_pc,
 245             o_output_instruction = fetch_output_instruction,
 246             o_output_state = fetch_output_st,
 247             i_reset_vector = reset_vector,
 248             i_mtvec = mtvec,
 249         )
 250         self.specials += fs
 251
 252         dc = Decoder()
 253
 254         cd = Instance("CPUDecoder", name="decoder",
 255             i_instruction = fetch_output_instruction,
 256             o_funct7 = dc.funct7,
 257             o_funct3 = dc.funct3,
 258             o_rd = dc.rd,
 259             o_rs1 = dc.rs1,
 260             o_rs2 = dc.rs2,
 261             o_immediate = dc.immediate,
 262             o_opcode = dc.opcode,
 263             o_decode_action = dc.act
 264         )
 265         self.specials += cd
 266
 267         register_rs1 = Signal(32)
 268         register_rs2 = Signal(32)
 269         self.comb += If(dc.rs1 == 0,
 270                         register_rs1.eq(0)
 271                      ).Else(
 272                         register_rs1.eq(self.registers[dc.rs1-1]))
 273         self.comb += If(dc.rs2 == 0,
 274                         register_rs2.eq(0)
 275                      ).Else(
 276                         register_rs2.eq(self.registers[dc.rs2-1]))
 277
 278         load_store_address = Signal(32)
 279         load_store_address_low_2 = Signal(2)
 280
 281         self.comb += load_store_address.eq(dc.immediate + register_rs1)
 282         self.comb += load_store_address_low_2.eq(
 283                             dc.immediate[:2] + register_rs1[:2])
 284
 285         load_store_misaligned = Signal()
 286
 287         lsa = self.get_ls_misaligned(load_store_misaligned, dc.funct3,
 288                                      load_store_address_low_2)
 289         self.comb += lsa
 290
 291         # XXX rwaddr not 31:2 any more
 292         self.comb += mi.rw_address.eq(load_store_address[2:])
 293
 294         unshifted_load_store_byte_mask = Signal(4)
 295
 296         self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(dc))
 297
 298         # XXX yuck.  this will cause migen simulation to fail
 299         # (however conversion to verilog works)
 300         self.comb += mi.rw_byte_mask.eq(
 301                 _Operator("<<", [unshifted_load_store_byte_mask,
 302                                         load_store_address_low_2]))
 303
 304         # XXX not obvious
 305         b3 = Mux(load_store_address_low_2[1],
 306                  Mux(load_store_address_low_2[0], register_rs2[0:8],
 307                                                   register_rs2[8:16]),
 308                  Mux(load_store_address_low_2[0], register_rs2[16:24],
 309                                                   register_rs2[24:32]))
 310         b2 = Mux(load_store_address_low_2[1], register_rs2[0:8],
 311                                               register_rs2[16:24])
 312         b1 = Mux(load_store_address_low_2[0], register_rs2[0:8],
 313                                               register_rs2[8:16])
 314         b0 = register_rs2[0:8]
 315
 316         self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
 317
 318         # XXX not obvious
 319         unmasked_loaded_value = Signal(32)
 320
 321         b0 = Mux(load_store_address_low_2[1],
 322                  Mux(load_store_address_low_2[0], mi.rw_data_out[24:32],
 323                                                   mi.rw_data_out[16:24]),
 324                  Mux(load_store_address_low_2[0], mi.rw_data_out[15:8],
 325                                                   mi.rw_data_out[0:8]))
 326         b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31],
 327                                               mi.rw_data_out[8:16])
 328         b23 = mi.rw_data_out[16:32]
 329
 330         self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
 331
 332         # XXX not obvious
 333         loaded_value = Signal(32)
 334
 335         b0 = unmasked_loaded_value[0:8]
 336         b1 = Mux(dc.funct3[0:2] == 0,
 337                 Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8),
 338                 unmasked_loaded_value[8:16])
 339         b2 = Mux(dc.funct3[1] == 0,
 340                 Replicate(~dc.funct3[2] &
 341                            Mux(dc.funct3[0], unmasked_loaded_value[15],
 342                                                   unmasked_loaded_value[7]),
 343                           16),
 344                 unmasked_loaded_value[16:32])
 345
 346         self.comb += loaded_value.eq(Cat(b0, b1, b2))
 347
 348         self.comb += mi.rw_active.eq(~self.reset
 349                         & (fetch_output_st == fetch_output_state_valid)
 350                         & ~load_store_misaligned
 351                         & ((dc.act & (DA.load | DA.store)) != 0))
 352
 353         self.comb += mi.rw_read_not_write.eq(~dc.opcode[5])
 354
 355         # alu
 356         alu_a = Signal(32)
 357         alu_b = Signal(32)
 358         alu_result = Signal(32)
 359
 360         self.comb += alu_a.eq(register_rs1)
 361         self.comb += alu_b.eq(Mux(dc.opcode[5],
 362                                   register_rs2,
 363                                   dc.immediate))
 364
 365         ali = Instance("cpu_alu", name="alu",
 366             i_funct7 = dc.funct7,
 367             i_funct3 = dc.funct3,
 368             i_opcode = dc.opcode,
 369             i_a = alu_a,
 370             i_b = alu_b,
 371             o_result = alu_result
 372         )
 373         self.specials += ali
 374
 375         lui_auipc_result = Signal(32)
 376         self.comb += lui_auipc_result.eq(Mux(dc.opcode[5],
 377                                              dc.immediate,
 378                                              dc.immediate + fetch_output_pc))
 379
 380         self.comb += fetch_target_pc.eq(Cat(0,
 381                     Mux(dc.opcode != OP.jalr,
 382                                 fetch_output_pc[1:32],
 383                                 register_rs1[1:32] + dc.immediate[1:32])))
 384
 385         misaligned_jump_target = Signal()
 386         self.comb += misaligned_jump_target.eq(fetch_target_pc[1])
 387
 388         branch_arg_a = Signal(32)
 389         branch_arg_b = Signal(32)
 390         self.comb += branch_arg_a.eq(Cat( register_rs1[0:31],
 391                                           register_rs1[31] ^ ~dc.funct3[1]))
 392         self.comb += branch_arg_b.eq(Cat( register_rs2[0:31],
 393                                           register_rs2[31] ^ ~dc.funct3[1]))
 394
 395         branch_taken = Signal()
 396         self.comb += branch_taken.eq(dc.funct3[0] ^
 397                                      Mux(dc.funct3[2],
 398                                          branch_arg_a < branch_arg_b,
 399                                          branch_arg_a == branch_arg_b))
 400
 401         m = M(self.comb, self.sync)
 402         mstatus = MStatus(self.comb, self.sync)
 403         mie = MIE(self.comb, self.sync)
 404
 405         misa = Misa(self.comb, self.sync)
 406
 407         #self.sync += If(self.reset, self.reset_to_initial(m, mstatus, mie,
 408         #                                                  registers))
 409
 410 if __name__ == "__main__":
 411     example = CPU()
 412     print(verilog.convert(example,
 413          {
 414            example.tty_write,
 415            example.tty_write_data,
 416            example.tty_write_busy,
 417            example.switch_2,
 418            example.switch_3,
 419            example.led_1,
 420            example.led_3,
 421            }))
 422
 423 """
 424
 425     parameter mvendorid = 32'b0;
 426     parameter marchid = 32'b0;
 427     parameter mimpid = 32'b0;
 428     parameter mhartid = 32'b0;
 429
 430     function [31:0] make_mstatus(input mstatus_tsr,
 431         input mstatus_tw,
 432         input mstatus_tvm,
 433         input mstatus_mxr,
 434         input mstatus_sum,
 435         input mstatus_mprv,
 436         input [1:0] mstatus_xs,
 437         input [1:0] mstatus_fs,
 438         input [1:0] mstatus_mpp,
 439         input mstatus_spp,
 440         input mstatus_mpie,
 441         input mstatus_spie,
 442         input mstatus_upie,
 443         input mstatus_mie,
 444         input mstatus_sie,
 445         input mstatus_uie);
 446     begin
 447         make_mstatus = {(mstatus_xs == 2'b11) | (mstatus_fs == 2'b11),
 448             8'b0,
 449             mstatus_tsr,
 450             mstatus_tw,
 451             mstatus_tvm,
 452             mstatus_mxr,
 453             mstatus_sum,
 454             mstatus_mprv,
 455             mstatus_xs,
 456             mstatus_fs,
 457             mstatus_mpp,
 458             2'b0,
 459             mstatus_spp,
 460             mstatus_mpie,
 461             1'b0,
 462             mstatus_spie,
 463             mstatus_upie,
 464             mstatus_mie,
 465             1'b0,
 466             mstatus_sie,
 467             mstatus_uie};
 468     end
 469     endfunction
 470
 471     wire mip_meip = 0; // TODO: implement external interrupts
 472     parameter mip_seip = 0;
 473     parameter mip_ueip = 0;
 474     wire mip_mtip = 0; // TODO: implement timer interrupts
 475     parameter mip_stip = 0;
 476     parameter mip_utip = 0;
 477     parameter mip_msip = 0;
 478     parameter mip_ssip = 0;
 479     parameter mip_usip = 0;
 480
 481     wire csr_op_is_valid;
 482
 483     function `fetch_action get_fetch_action(
 484         input `fetch_output_state fetch_output_state,
 485         input `decode_action decode_action,
 486         input load_store_misaligned,
 487         input memory_interface_rw_address_valid,
 488         input memory_interface_rw_wait,
 489         input branch_taken,
 490         input misaligned_jump_target,
 491         input csr_op_is_valid
 492         );
 493     begin
 494         case(fetch_output_state)
 495         `fetch_output_state_empty:
 496             get_fetch_action = `fetch_action_default;
 497         `fetch_output_state_trap:
 498             get_fetch_action = `fetch_action_ack_trap;
 499         `fetch_output_state_valid: begin
 500             if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 501                 get_fetch_action = `fetch_action_error_trap;
 502             end
 503             else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 504                 get_fetch_action = `fetch_action_noerror_trap;
 505             end
 506             else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
 507                 if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
 508                     get_fetch_action = `fetch_action_error_trap;
 509                 end
 510                 else if(memory_interface_rw_wait) begin
 511                     get_fetch_action = `fetch_action_wait;
 512                 end
 513                 else begin
 514                     get_fetch_action = `fetch_action_default;
 515                 end
 516             end
 517             else if((decode_action & `decode_action_fence_i) != 0) begin
 518                 get_fetch_action = `fetch_action_fence;
 519             end
 520             else if((decode_action & `decode_action_branch) != 0) begin
 521                 if(branch_taken) begin
 522                     if(misaligned_jump_target) begin
 523                         get_fetch_action = `fetch_action_error_trap;
 524                     end
 525                     else begin
 526                         get_fetch_action = `fetch_action_jump;
 527                     end
 528                 end
 529                 else
 530                 begin
 531                     get_fetch_action = `fetch_action_default;
 532                 end
 533             end
 534             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 535                 if(misaligned_jump_target) begin
 536                     get_fetch_action = `fetch_action_error_trap;
 537                 end
 538                 else begin
 539                     get_fetch_action = `fetch_action_jump;
 540                 end
 541             end
 542             else if((decode_action & `decode_action_csr) != 0) begin
 543                 if(csr_op_is_valid)
 544                     get_fetch_action = `fetch_action_default;
 545                 else
 546                     get_fetch_action = `fetch_action_error_trap;
 547             end
 548             else begin
 549                 get_fetch_action = `fetch_action_default;
 550             end
 551         end
 552         default:
 553             get_fetch_action = 32'hXXXXXXXX;
 554         endcase
 555     end
 556     endfunction
 557
 558     assign fetch_action = get_fetch_action(
 559         fetch_output_state,
 560         decode_action,
 561         load_store_misaligned,
 562         memory_interface_rw_address_valid,
 563         memory_interface_rw_wait,
 564         branch_taken,
 565         misaligned_jump_target,
 566         csr_op_is_valid
 567         );
 568
 569     task handle_trap;
 570     begin
 571         mstatus_mpie = mstatus_mie;
 572         mstatus_mie = 0;
 573         mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
 574         if(fetch_action == `fetch_action_ack_trap) begin
 575             mcause = `cause_instruction_access_fault;
 576         end
 577         else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 578             mcause = `cause_illegal_instruction;
 579         end
 580         else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 581             mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
 582         end
 583         else if((decode_action & `decode_action_load) != 0) begin
 584             if(load_store_misaligned)
 585                 mcause = `cause_load_address_misaligned;
 586             else
 587                 mcause = `cause_load_access_fault;
 588         end
 589         else if((decode_action & `decode_action_store) != 0) begin
 590             if(load_store_misaligned)
 591                 mcause = `cause_store_amo_address_misaligned;
 592             else
 593                 mcause = `cause_store_amo_access_fault;
 594         end
 595         else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
 596             mcause = `cause_instruction_address_misaligned;
 597         end
 598         else begin
 599             mcause = `cause_illegal_instruction;
 600         end
 601     end
 602     endtask
 603
 604     wire [11:0] csr_number = decoder_immediate;
 605     wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
 606     wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
 607     wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
 608
 609     function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
 610     begin
 611         case(csr_number)
 612         `csr_ustatus,
 613         `csr_fflags,
 614         `csr_frm,
 615         `csr_fcsr,
 616         `csr_uie,
 617         `csr_utvec,
 618         `csr_uscratch,
 619         `csr_uepc,
 620         `csr_ucause,
 621         `csr_utval,
 622         `csr_uip,
 623         `csr_sstatus,
 624         `csr_sedeleg,
 625         `csr_sideleg,
 626         `csr_sie,
 627         `csr_stvec,
 628         `csr_scounteren,
 629         `csr_sscratch,
 630         `csr_sepc,
 631         `csr_scause,
 632         `csr_stval,
 633         `csr_sip,
 634         `csr_satp,
 635         `csr_medeleg,
 636         `csr_mideleg,
 637         `csr_dcsr,
 638         `csr_dpc,
 639         `csr_dscratch:
 640             get_csr_op_is_valid = 0;
 641         `csr_cycle,
 642         `csr_time,
 643         `csr_instret,
 644         `csr_cycleh,
 645         `csr_timeh,
 646         `csr_instreth,
 647         `csr_mvendorid,
 648         `csr_marchid,
 649         `csr_mimpid,
 650         `csr_mhartid:
 651             get_csr_op_is_valid = ~csr_writes;
 652         `csr_misa,
 653         `csr_mstatus,
 654         `csr_mie,
 655         `csr_mtvec,
 656         `csr_mscratch,
 657         `csr_mepc,
 658         `csr_mcause,
 659         `csr_mip:
 660             get_csr_op_is_valid = 1;
 661         `csr_mcounteren,
 662         `csr_mtval,
 663         `csr_mcycle,
 664         `csr_minstret,
 665         `csr_mcycleh,
 666         `csr_minstreth:
 667             // TODO: CSRs not implemented yet
 668             get_csr_op_is_valid = 0;
 669         endcase
 670     end
 671     endfunction
 672
 673     assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
 674
 675     wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
 676     wire [63:0] time_counter = 0; // TODO: implement time_counter
 677     wire [63:0] instret_counter = 0; // TODO: implement instret_counter
 678
 679     always @(posedge clk) begin:main_block
 680         if(reset) begin
 681             reset_to_initial();
 682             disable main_block;
 683         end
 684         case(fetch_output_state)
 685         `fetch_output_state_empty: begin
 686         end
 687         `fetch_output_state_trap: begin
 688             handle_trap();
 689         end
 690         `fetch_output_state_valid: begin:valid
 691             if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
 692                 handle_trap();
 693             end
 694             else if((decode_action & `decode_action_load) != 0) begin
 695                 if(~memory_interface_rw_wait)
 696                     write_register(decoder_rd, loaded_value);
 697             end
 698             else if((decode_action & `decode_action_op_op_imm) != 0) begin
 699                 write_register(decoder_rd, alu_result);
 700             end
 701             else if((decode_action & `decode_action_lui_auipc) != 0) begin
 702                 write_register(decoder_rd, lui_auipc_result);
 703             end
 704             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 705                 write_register(decoder_rd, fetch_output_pc + 4);
 706             end
 707             else if((decode_action & `decode_action_csr) != 0) begin:csr
 708                 reg [31:0] csr_output_value;
 709                 reg [31:0] csr_written_value;
 710                 csr_output_value = 32'hXXXXXXXX;
 711                 csr_written_value = 32'hXXXXXXXX;
 712                 case(csr_number)
 713                 `csr_cycle: begin
 714                     csr_output_value = cycle_counter[31:0];
 715                 end
 716                 `csr_time: begin
 717                     csr_output_value = time_counter[31:0];
 718                 end
 719                 `csr_instret: begin
 720                     csr_output_value = instret_counter[31:0];
 721                 end
 722                 `csr_cycleh: begin
 723                     csr_output_value = cycle_counter[63:32];
 724                 end
 725                 `csr_timeh: begin
 726                     csr_output_value = time_counter[63:32];
 727                 end
 728                 `csr_instreth: begin
 729                     csr_output_value = instret_counter[63:32];
 730                 end
 731                 `csr_mvendorid: begin
 732                     csr_output_value = mvendorid;
 733                 end
 734                 `csr_marchid: begin
 735                     csr_output_value = marchid;
 736                 end
 737                 `csr_mimpid: begin
 738                     csr_output_value = mimpid;
 739                 end
 740                 `csr_mhartid: begin
 741                     csr_output_value = mhartid;
 742                 end
 743                 `csr_misa: begin
 744                     csr_output_value = misa;
 745                 end
 746                 `csr_mstatus: begin
 747                     csr_output_value = make_mstatus(mstatus_tsr,
 748                                                     mstatus_tw,
 749                                                     mstatus_tvm,
 750                                                     mstatus_mxr,
 751                                                     mstatus_sum,
 752                                                     mstatus_mprv,
 753                                                     mstatus_xs,
 754                                                     mstatus_fs,
 755                                                     mstatus_mpp,
 756                                                     mstatus_spp,
 757                                                     mstatus_mpie,
 758                                                     mstatus_spie,
 759                                                     mstatus_upie,
 760                                                     mstatus_mie,
 761                                                     mstatus_sie,
 762                                                     mstatus_uie);
 763                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 764                     if(csr_writes) begin
 765                         mstatus_mpie = csr_written_value[7];
 766                         mstatus_mie = csr_written_value[3];
 767                     end
 768                 end
 769                 `csr_mie: begin
 770                     csr_output_value = 0;
 771                     csr_output_value[11] = mie_meie;
 772                     csr_output_value[9] = mie_seie;
 773                     csr_output_value[8] = mie_ueie;
 774                     csr_output_value[7] = mie_mtie;
 775                     csr_output_value[5] = mie_stie;
 776                     csr_output_value[4] = mie_utie;
 777                     csr_output_value[3] = mie_msie;
 778                     csr_output_value[1] = mie_ssie;
 779                     csr_output_value[0] = mie_usie;
 780                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 781                     if(csr_writes) begin
 782                         mie_meie = csr_written_value[11];
 783                         mie_mtie = csr_written_value[7];
 784                         mie_msie = csr_written_value[3];
 785                     end
 786                 end
 787                 `csr_mtvec: begin
 788                     csr_output_value = mtvec;
 789                 end
 790                 `csr_mscratch: begin
 791                     csr_output_value = mscratch;
 792                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 793                     if(csr_writes)
 794                         mscratch = csr_written_value;
 795                 end
 796                 `csr_mepc: begin
 797                     csr_output_value = mepc;
 798                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 799                     if(csr_writes)
 800                         mepc = csr_written_value;
 801                 end
 802                 `csr_mcause: begin
 803                     csr_output_value = mcause;
 804                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 805                     if(csr_writes)
 806                         mcause = csr_written_value;
 807                 end
 808                 `csr_mip: begin
 809                     csr_output_value = 0;
 810                     csr_output_value[11] = mip_meip;
 811                     csr_output_value[9] = mip_seip;
 812                     csr_output_value[8] = mip_ueip;
 813                     csr_output_value[7] = mip_mtip;
 814                     csr_output_value[5] = mip_stip;
 815                     csr_output_value[4] = mip_utip;
 816                     csr_output_value[3] = mip_msip;
 817                     csr_output_value[1] = mip_ssip;
 818                     csr_output_value[0] = mip_usip;
 819                 end
 820                 endcase
 821                 if(csr_reads)
 822                     write_register(decoder_rd, csr_output_value);
 823             end
 824             else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin
 825                 // do nothing
 826             end
 827         end
 828         endcase
 829     end
 830
 831 endmodule
 832 """
 833