debug_rom/debug_rom.S

   1 # This code should be functional. Doesn't have to be optimal.
   2 # I'm writing it to prove that it can be done.
   3
   4 #include "riscv/encoding.h"
   5
   6 # TODO: Update these constants once they're finalized in the doc.
   7
   8 #define DEBUG_RAM               0x400
   9 #define DEBUG_RAM_SIZE          64
  10
  11 #define SETHALTNOT              0x100
  12 #define CLEARDEBINT             0x108
  13
  14         .global entry
  15         .global resume
  16         .global exception
  17
  18         # Automatically called when Debug Mode is first entered.
  19 entry:  j       _entry
  20         # Should be called by Debug RAM code that has finished execution and
  21         # wants to return to Debug Mode.
  22 resume:
  23         j       _resume
  24 exception:
  25         # Set the last word of Debug RAM to all ones, to indicate that we hit
  26         # an exception.
  27         li      s0, ~0
  28         j       _resume2
  29
  30 _resume:
  31         li      s0, 0
  32 _resume2:
  33         # Clear debug interrupt.
  34         csrr    s1, CSR_MHARTID
  35         sw      s1, CLEARDEBINT(zero)
  36         fence
  37
  38         # Restore s1.
  39         csrr    s1, CSR_MISA
  40         bltz    s1, restore_not_32
  41 restore_32:
  42         lw      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
  43         j       check_halt
  44 restore_not_32:
  45         slli    s1, s1, 1
  46         bltz    s1, restore_128
  47 restore_64:
  48         ld      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 8)(zero)
  49         j       check_halt
  50 restore_128:
  51         nop     #lq      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero)
  52
  53         # s0 contains ~0 if we got here through an exception, and 0 otherwise.
  54         # Store this to the last word in Debug RAM so the debugger can tell if
  55         # an exception occurred.
  56         sw      s0, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
  57
  58 check_halt:
  59         csrr    s0, CSR_DCSR
  60         andi    s0, s0, DCSR_HALT
  61         beqz    s0, exit
  62         j       wait_for_interrupt
  63
  64 exit:
  65         # Restore s0.
  66         csrr    s0, CSR_DSCRATCH
  67         .word   0x79200073      # TODO: dret
  68
  69 _entry:
  70         # Save s0 in DSCRATCH
  71         csrw    CSR_DSCRATCH, s0
  72
  73         # Check why we're here
  74         csrr    s0, CSR_DCSR
  75         # cause is in bits 2:0 of dcsr
  76         andi    s0, s0, DCSR_CAUSE
  77         addi    s0, s0, -DCSR_CAUSE_DEBUGINT
  78         bnez    s0, spontaneous_halt
  79
  80 jdebugram:
  81         # Save s1 so that the debug program can use two registers.
  82         fence.i
  83         csrr    s0, CSR_MISA
  84         bltz    s0, save_not_32
  85 save_32:
  86         sw      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
  87         jr      zero, DEBUG_RAM
  88 save_not_32:
  89         slli    s0, s0, 1
  90         bltz    s0, save_128
  91 save_64:
  92         sd      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 8)(zero)
  93         jr      zero, DEBUG_RAM
  94 save_128:
  95         nop     #sq      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero)
  96         jr      zero, DEBUG_RAM
  97
  98 spontaneous_halt:
  99         csrr    s0, CSR_MHARTID
 100         sw      s0, SETHALTNOT(zero)
 101         csrsi   CSR_DCSR, DCSR_HALT
 102
 103 wait_for_interrupt:
 104         csrr    s0, CSR_DCSR
 105         andi    s0, s0, DCSR_DEBUGINT
 106         beqz    s0, wait_for_interrupt
 107
 108         j       jdebugram