debug_rom/debug_rom.S

   1 # This code should be functional. Doesn't have to be optimal.
   2 # I'm writing it to prove that it can be done.
   3
   4 #include "riscv/encoding.h"
   5
   6 # TODO: Update these constants once they're finalized in the doc.
   7
   8 #define DCSR                    0x790
   9 #define DCSR_CAUSE_DEBINT       3
  10 #define DCSR_HALT_OFFSET        3
  11 #define DCSR_DEBUGINT_OFFSET    10
  12
  13 #define DSCRATCH                0x792
  14
  15 #define DEBUG_RAM               0x400
  16 #define DEBUG_RAM_SIZE          64
  17
  18 #define SETHALTNOT              0x100
  19 #define CLEARDEBINT             0x108
  20
  21         .global entry
  22         .global resume
  23
  24         # Automatically called when Debug Mode is first entered.
  25 entry:  j       _entry
  26         # Should be called by Debug RAM code that has finished execution and
  27         # wants to return to Debug Mode.
  28 resume:
  29         # Clear debug interrupt.
  30 clear_debint:
  31         csrr    s1, CSR_MHARTID
  32         sw      s1, CLEARDEBINT(zero)
  33         fence
  34
  35         # Restore s1.
  36         csrr    s1, CSR_MISA
  37         bltz    s1, restore_not_32
  38 restore_32:
  39         lw      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
  40         j       check_halt
  41 restore_not_32:
  42         slli    s1, s1, 1
  43         bltz    s1, restore_128
  44 restore_64:
  45         ld      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 8)(zero)
  46         j       check_halt
  47 restore_128:
  48         nop     #lq      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero)
  49
  50 check_halt:
  51         csrr    s0, DCSR
  52         andi    s0, s0, (1<<DCSR_HALT_OFFSET)
  53         beqz    s0, exit
  54         j       wait_for_interrupt
  55
  56 exit:
  57         # Restore s0.
  58         csrr    s0, DSCRATCH
  59         # TODO: dret?
  60         mret
  61
  62
  63 _entry:
  64         # Save s0 in DSCRATCH
  65         csrw    DSCRATCH, s0
  66
  67         # Check why we're here
  68         csrr    s0, DCSR
  69         # cause is in bits 2:0 of dcsr
  70         andi    s0, s0, 7
  71         addi    s0, s0, -DCSR_CAUSE_DEBINT
  72         bnez    s0, spontaneous_halt
  73
  74 jdebugram:
  75         # Save s1 so that the debug program can use two registers.
  76         csrr    s0, CSR_MISA
  77         bltz    s0, save_not_32
  78 save_32:
  79         sw      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
  80         jr      zero, DEBUG_RAM
  81 save_not_32:
  82         slli    s0, s0, 1
  83         bltz    s0, save_128
  84 save_64:
  85         sd      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 8)(zero)
  86         jr      zero, DEBUG_RAM
  87 save_128:
  88         nop     #sq      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero)
  89         jr      zero, DEBUG_RAM
  90
  91 spontaneous_halt:
  92         csrr    s0, CSR_MHARTID
  93         sw      s0, SETHALTNOT(zero)
  94         csrsi   DCSR, (1<<DCSR_HALT_OFFSET)
  95
  96 wait_for_interrupt:
  97         csrr    s0, DCSR
  98         andi    s0, s0, (1<<DCSR_DEBUGINT_OFFSET)
  99         beqz    s0, wait_for_interrupt
 100
 101         j       jdebugram