3 #include "debug_module.h"
4 #include "debug_defines.h"
8 #include "debug_rom/debug_rom.h"
16 ///////////////////////// debug_module_data_t
18 debug_module_data_t::debug_module_data_t()
20 memset(data
, 0, sizeof(data
));
23 bool debug_module_data_t::load(reg_t addr
, size_t len
, uint8_t* bytes
)
25 D(fprintf(stderr
, "debug_module_data_t load 0x%lx bytes at 0x%lx\n", len
,
28 if (addr
+ len
< sizeof(data
)) {
29 memcpy(bytes
, data
+ addr
, len
);
33 fprintf(stderr
, "ERROR: invalid load from debug_module_data_t: %zd bytes at 0x%016"
34 PRIx64
"\n", len
, addr
);
39 bool debug_module_data_t::store(reg_t addr
, size_t len
, const uint8_t* bytes
)
41 D(fprintf(stderr
, "debug_module_data_t store 0x%lx bytes at 0x%lx\n", len
,
44 if (addr
+ len
< sizeof(data
)) {
45 memcpy(data
+ addr
, bytes
, len
);
49 fprintf(stderr
, "ERROR: invalid store to debug_module_data_t: %zd bytes at 0x%016"
50 PRIx64
"\n", len
, addr
);
54 uint32_t debug_module_data_t::read32(reg_t addr
) const
56 assert(addr
+ 4 <= sizeof(data
));
58 (data
[addr
+ 1] << 8) |
59 (data
[addr
+ 2] << 16) |
60 (data
[addr
+ 3] << 24);
63 void debug_module_data_t::write32(reg_t addr
, uint32_t value
)
65 fprintf(stderr
, "debug_module_data_t::write32(0x%lx, 0x%x)\n", addr
, value
);
66 assert(addr
+ 4 <= sizeof(data
));
67 data
[addr
] = value
& 0xff;
68 data
[addr
+ 1] = (value
>> 8) & 0xff;
69 data
[addr
+ 2] = (value
>> 16) & 0xff;
70 data
[addr
+ 3] = (value
>> 24) & 0xff;
73 ///////////////////////// debug_module_t
75 debug_module_t::debug_module_t(sim_t
*sim
) : sim(sim
)
78 dmcontrol
.version
= 1;
80 for (unsigned i
= 0; i
< DEBUG_ROM_ENTRY_SIZE
/ 4; i
++) {
81 write32(debug_rom_entry
, i
, jal(ZERO
, 0));
85 for (unsigned i
= 0; i
< progsize
; i
++) {
91 void debug_module_t::reset()
93 for (unsigned i
= 0; i
< sim
->nprocs(); i
++) {
94 processor_t
*proc
= sim
->get_core(i
);
96 proc
->halt_request
= false;
100 dmcontrol
.authenticated
= 1;
101 dmcontrol
.version
= 1;
102 dmcontrol
.authtype
= dmcontrol
.AUTHTYPE_NOAUTH
;
105 abstractcs
.datacount
= sizeof(dmdata
.data
) / 4;
108 void debug_module_t::add_device(bus_t
*bus
) {
109 bus
->add_device(DEBUG_START
, this);
110 bus
->add_device(DEBUG_EXCHANGE
, &dmdata
);
113 bool debug_module_t::load(reg_t addr
, size_t len
, uint8_t* bytes
)
115 D(fprintf(stderr
, "load 0x%lx bytes at 0x%lx\n",
117 addr
= DEBUG_START
+ addr
;
119 if (addr
>= DEBUG_ROM_ENTRY
&&
120 addr
< DEBUG_ROM_ENTRY
+ DEBUG_ROM_ENTRY_SIZE
) {
121 halted
[(addr
- DEBUG_ROM_ENTRY
) / 4] = true;
122 memcpy(bytes
, debug_rom_entry
+ addr
- DEBUG_ROM_ENTRY
, len
);
124 if (read32(debug_rom_entry
, dmcontrol
.hartsel
) == jal(ZERO
, 0)) {
125 // We're here in an infinite loop. That means that whatever abstract
126 // command has complete.
127 abstractcs
.busy
= false;
132 // Restore the jump-to-self loop.
133 write32(debug_rom_entry
, dmcontrol
.hartsel
, jal(ZERO
, 0));
135 if (addr
>= DEBUG_ROM_CODE
&&
136 addr
< DEBUG_ROM_CODE
+ DEBUG_ROM_CODE_SIZE
) {
137 memcpy(bytes
, debug_rom_code
+ addr
- DEBUG_ROM_CODE
, len
);
141 if (addr
>= DEBUG_ROM_EXCEPTION
&&
142 addr
< DEBUG_ROM_EXCEPTION
+ DEBUG_ROM_EXCEPTION_SIZE
) {
143 memcpy(bytes
, debug_rom_exception
+ addr
- DEBUG_ROM_EXCEPTION
, len
);
144 if (abstractcs
.cmderr
== abstractcs
.CMDERR_NONE
) {
145 abstractcs
.cmderr
= abstractcs
.CMDERR_EXCEPTION
;
150 fprintf(stderr
, "ERROR: invalid load from debug module: %zd bytes at 0x%016"
151 PRIx64
"\n", len
, addr
);
156 bool debug_module_t::store(reg_t addr
, size_t len
, const uint8_t* bytes
)
158 addr
= DEBUG_START
+ addr
;
160 fprintf(stderr
, "ERROR: invalid store to debug module: %zd bytes at 0x%016"
161 PRIx64
"\n", len
, addr
);
165 void debug_module_t::write32(uint8_t *memory
, unsigned int index
, uint32_t value
)
167 uint8_t* base
= memory
+ index
* 4;
168 base
[0] = value
& 0xff;
169 base
[1] = (value
>> 8) & 0xff;
170 base
[2] = (value
>> 16) & 0xff;
171 base
[3] = (value
>> 24) & 0xff;
174 uint32_t debug_module_t::read32(uint8_t *memory
, unsigned int index
)
176 uint8_t* base
= memory
+ index
* 4;
177 uint32_t value
= ((uint32_t) base
[0]) |
178 (((uint32_t) base
[1]) << 8) |
179 (((uint32_t) base
[2]) << 16) |
180 (((uint32_t) base
[3]) << 24);
184 processor_t
*debug_module_t::current_proc() const
186 processor_t
*proc
= NULL
;
188 proc
= sim
->get_core(dmcontrol
.hartsel
);
189 } catch (const std::out_of_range
&) {
194 bool debug_module_t::dmi_read(unsigned address
, uint32_t *value
)
197 D(fprintf(stderr
, "dmi_read(0x%x) -> ", address
));
198 if (address
>= DMI_DATA0
&& address
< DMI_DATA0
+ abstractcs
.datacount
) {
199 result
= dmdata
.read32(4 * (address
- DMI_DATA0
));
200 } else if (address
>= DMI_IBUF0
&& address
< DMI_IBUF0
+ progsize
) {
201 result
= ibuf
[address
- DMI_IBUF0
];
206 processor_t
*proc
= current_proc();
208 if (halted
[dmcontrol
.hartsel
]) {
209 dmcontrol
.hartstatus
= dmcontrol
.HARTSTATUS_HALTED
;
211 dmcontrol
.hartstatus
= dmcontrol
.HARTSTATUS_RUNNING
;
213 dmcontrol
.haltreq
= proc
->halt_request
;
215 dmcontrol
.hartstatus
= dmcontrol
.HARTSTATUS_NOTEXIST
;
217 result
= set_field(result
, DMI_DMCONTROL_HALTREQ
, dmcontrol
.haltreq
);
218 result
= set_field(result
, DMI_DMCONTROL_RESET
, dmcontrol
.reset
);
219 result
= set_field(result
, DMI_DMCONTROL_DMACTIVE
, dmcontrol
.dmactive
);
220 result
= set_field(result
, DMI_DMCONTROL_HARTSTATUS
, dmcontrol
.hartstatus
);
221 result
= set_field(result
, DMI_DMCONTROL_HARTSEL
, dmcontrol
.hartsel
);
222 result
= set_field(result
, DMI_DMCONTROL_AUTHENTICATED
, dmcontrol
.authenticated
);
223 result
= set_field(result
, DMI_DMCONTROL_AUTHBUSY
, dmcontrol
.authbusy
);
224 result
= set_field(result
, DMI_DMCONTROL_AUTHTYPE
, dmcontrol
.authtype
);
225 result
= set_field(result
, DMI_DMCONTROL_VERSION
, dmcontrol
.version
);
229 result
= set_field(result
, DMI_ABSTRACTCS_AUTOEXEC7
, abstractcs
.autoexec7
);
230 result
= set_field(result
, DMI_ABSTRACTCS_AUTOEXEC6
, abstractcs
.autoexec6
);
231 result
= set_field(result
, DMI_ABSTRACTCS_AUTOEXEC5
, abstractcs
.autoexec5
);
232 result
= set_field(result
, DMI_ABSTRACTCS_AUTOEXEC4
, abstractcs
.autoexec4
);
233 result
= set_field(result
, DMI_ABSTRACTCS_AUTOEXEC3
, abstractcs
.autoexec3
);
234 result
= set_field(result
, DMI_ABSTRACTCS_AUTOEXEC2
, abstractcs
.autoexec2
);
235 result
= set_field(result
, DMI_ABSTRACTCS_AUTOEXEC1
, abstractcs
.autoexec1
);
236 result
= set_field(result
, DMI_ABSTRACTCS_AUTOEXEC0
, abstractcs
.autoexec0
);
237 result
= set_field(result
, DMI_ABSTRACTCS_CMDERR
, abstractcs
.cmderr
);
238 result
= set_field(result
, DMI_ABSTRACTCS_BUSY
, abstractcs
.busy
);
239 result
= set_field(result
, DMI_ABSTRACTCS_DATACOUNT
, abstractcs
.datacount
);
242 result
= progsize
<< DMI_ACCESSCS_PROGSIZE_OFFSET
;
248 D(fprintf(stderr
, "error\n"));
252 D(fprintf(stderr
, "0x%x\n", result
));
257 bool debug_module_t::perform_abstract_command(uint32_t command
)
259 if (abstractcs
.cmderr
!= abstractcs
.CMDERR_NONE
)
261 if (abstractcs
.busy
) {
262 abstractcs
.cmderr
= abstractcs
.CMDERR_BUSY
;
266 if ((command
>> 24) == 0) {
268 unsigned size
= get_field(command
, AC_ACCESS_REGISTER_SIZE
);
269 bool write
= get_field(command
, AC_ACCESS_REGISTER_WRITE
);
270 unsigned regno
= get_field(command
, AC_ACCESS_REGISTER_REGNO
);
272 if (regno
< 0x1000 || regno
>= 0x1020) {
273 abstractcs
.cmderr
= abstractcs
.CMDERR_NOTSUP
;
277 unsigned regnum
= regno
- 0x1000;
279 if (!halted
[dmcontrol
.hartsel
]) {
280 abstractcs
.cmderr
= abstractcs
.CMDERR_HALTRESUME
;
287 write32(debug_rom_code
, 0, lw(regnum
, ZERO
, DEBUG_EXCHANGE
));
289 write32(debug_rom_code
, 0, sw(regnum
, ZERO
, DEBUG_EXCHANGE
));
293 write32(debug_rom_code
, 0, ld(regnum
, ZERO
, DEBUG_EXCHANGE
));
295 write32(debug_rom_code
, 0, sd(regnum
, ZERO
, DEBUG_EXCHANGE
));
300 write32(debug_rom_code, 0, lq(regnum, ZERO, DEBUG_EXCHANGE));
302 write32(debug_rom_code, 0, sq(regnum, ZERO, DEBUG_EXCHANGE));
306 abstractcs
.cmderr
= abstractcs
.CMDERR_NOTSUP
;
309 write32(debug_rom_code
, 1, ebreak());
311 write32(debug_rom_entry
, dmcontrol
.hartsel
,
312 jal(ZERO
, DEBUG_ROM_CODE
- (DEBUG_ROM_ENTRY
+ 4 * dmcontrol
.hartsel
)));
313 write32(debug_rom_exception
, dmcontrol
.hartsel
,
314 jal(ZERO
, (DEBUG_ROM_ENTRY
+ 4 * dmcontrol
.hartsel
) - DEBUG_ROM_EXCEPTION
));
315 abstractcs
.busy
= true;
317 abstractcs
.cmderr
= abstractcs
.CMDERR_NOTSUP
;
322 bool debug_module_t::dmi_write(unsigned address
, uint32_t value
)
324 D(fprintf(stderr
, "dmi_write(0x%x, 0x%x)\n", address
, value
));
325 if (address
>= DMI_DATA0
&& address
< DMI_DATA0
+ abstractcs
.datacount
) {
326 dmdata
.write32(4 * (address
- DMI_DATA0
), value
);
328 } else if (address
>= DMI_IBUF0
&& address
< DMI_IBUF0
+ progsize
) {
329 ibuf
[address
- DMI_IBUF0
] = value
;
335 dmcontrol
.dmactive
= get_field(value
, DMI_DMCONTROL_DMACTIVE
);
336 if (dmcontrol
.dmactive
) {
337 dmcontrol
.haltreq
= get_field(value
, DMI_DMCONTROL_HALTREQ
);
338 dmcontrol
.reset
= get_field(value
, DMI_DMCONTROL_RESET
);
339 dmcontrol
.hartsel
= get_field(value
, DMI_DMCONTROL_HARTSEL
);
343 processor_t
*proc
= current_proc();
345 proc
->halt_request
= dmcontrol
.haltreq
;
351 return perform_abstract_command(value
);
354 abstractcs
.autoexec7
= get_field(value
, DMI_ABSTRACTCS_AUTOEXEC7
);
355 abstractcs
.autoexec6
= get_field(value
, DMI_ABSTRACTCS_AUTOEXEC6
);
356 abstractcs
.autoexec5
= get_field(value
, DMI_ABSTRACTCS_AUTOEXEC5
);
357 abstractcs
.autoexec4
= get_field(value
, DMI_ABSTRACTCS_AUTOEXEC4
);
358 abstractcs
.autoexec3
= get_field(value
, DMI_ABSTRACTCS_AUTOEXEC3
);
359 abstractcs
.autoexec2
= get_field(value
, DMI_ABSTRACTCS_AUTOEXEC2
);
360 abstractcs
.autoexec1
= get_field(value
, DMI_ABSTRACTCS_AUTOEXEC1
);
361 abstractcs
.autoexec0
= get_field(value
, DMI_ABSTRACTCS_AUTOEXEC0
);
362 if (get_field(value
, DMI_ABSTRACTCS_CMDERR
) == abstractcs
.CMDERR_NONE
) {
363 abstractcs
.cmderr
= abstractcs
.CMDERR_NONE
;