Abstract register read mostly working.
authorTim Newsome <tim@sifive.com>
Mon, 13 Feb 2017 17:53:23 +0000 (09:53 -0800)
committerTim Newsome <tim@sifive.com>
Mon, 13 Feb 2017 17:53:23 +0000 (09:53 -0800)
commit1a623701469c08e72685d44a4ebed9157ab4bfe2
tree724d7adefffbe2ffc4ea0f42b1be28689ba7f936
parentf7f110504072dc601a24a4391cbf3b0091a47a12
Abstract register read mostly working.

Fails with not supported for 128-bit.
Fails with exception (on rv32) with 64-bit.
Succeeds (on rv32) with 32-bit.
riscv/debug_module.cc
riscv/debug_module.h
riscv/decode.h
riscv/jtag_dtm.cc
riscv/processor.cc
riscv/sim.cc