Abstract register read mostly working.

[riscv-isa-sim.git] / riscv / decode.h

diff --git a/riscv/decode.h b/riscv/decode.h
index c34b07eddbbae6fbf9de925517f4427d919e0388..e78a587ef7da9d8b9ef848e2ddc0bc71417d4ba1 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -227,11 +227,17 @@ private:
 
 #define DEBUG_START             0x20000
 #define DEBUG_ROM_ENTRY         DEBUG_START
-#define DEBUG_ROM_CODE          (DEBUG_ROM_ENTRY + 1024 * 4)
-#define DEBUG_ROM_EXCEPTION     (DEBUG_ROM_CODE + 4)
-#define DEBUG_RAM_START         (DEBUG_ROM_EXCEPTION + 256)
+#define DEBUG_ROM_ENTRY_SIZE    (1024 * 4)
+#define DEBUG_ROM_CODE          (DEBUG_ROM_ENTRY + DEBUG_ROM_ENTRY_SIZE)
+#define DEBUG_ROM_CODE_SIZE     256
+#define DEBUG_ROM_EXCEPTION     (DEBUG_ROM_CODE + DEBUG_ROM_CODE_SIZE)
+#define DEBUG_ROM_EXCEPTION_SIZE        4
+#define DEBUG_RAM_START         (DEBUG_ROM_EXCEPTION + DEBUG_ROM_EXCEPTION_SIZE)
 #define DEBUG_RAM_SIZE          64
 #define DEBUG_RAM_END           (DEBUG_RAM_START + DEBUG_RAM_SIZE)
 #define DEBUG_END               DEBUG_RAM_END
 
+#define DEBUG_EXCHANGE          0x400
+#define DEBUG_EXCHANGE_SIZE     0x20
+
 #endif