Abstract register read mostly working.
[riscv-isa-sim.git] / riscv / processor.cc
1 // See LICENSE for license details.
2
3 #include "processor.h"
4 #include "extension.h"
5 #include "common.h"
6 #include "config.h"
7 #include "sim.h"
8 #include "mmu.h"
9 #include "disasm.h"
10 #include <cinttypes>
11 #include <cmath>
12 #include <cstdlib>
13 #include <iostream>
14 #include <assert.h>
15 #include <limits.h>
16 #include <stdexcept>
17 #include <algorithm>
18
19 #undef STATE
20 #define STATE state
21
22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
23 bool halt_on_reset)
24 : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
25 halt_on_reset(halt_on_reset)
26 {
27 parse_isa_string(isa);
28 register_base_instructions();
29
30 mmu = new mmu_t(sim, this);
31 disassembler = new disassembler_t(max_xlen);
32
33 reset();
34 }
35
36 processor_t::~processor_t()
37 {
38 #ifdef RISCV_ENABLE_HISTOGRAM
39 if (histogram_enabled)
40 {
41 fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
42 for (auto it : pc_histogram)
43 fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
44 }
45 #endif
46
47 delete mmu;
48 delete disassembler;
49 }
50
51 static void bad_isa_string(const char* isa)
52 {
53 fprintf(stderr, "error: bad --isa option %s\n", isa);
54 abort();
55 }
56
57 void processor_t::parse_isa_string(const char* str)
58 {
59 std::string lowercase, tmp;
60 for (const char *r = str; *r; r++)
61 lowercase += std::tolower(*r);
62
63 const char* p = lowercase.c_str();
64 const char* all_subsets = "imafdc";
65
66 max_xlen = 64;
67 isa = reg_t(2) << 62;
68
69 if (strncmp(p, "rv32", 4) == 0)
70 max_xlen = 32, isa = reg_t(1) << 30, p += 4;
71 else if (strncmp(p, "rv64", 4) == 0)
72 p += 4;
73 else if (strncmp(p, "rv", 2) == 0)
74 p += 2;
75
76 if (!*p) {
77 p = all_subsets;
78 } else if (*p == 'g') { // treat "G" as "IMAFD"
79 tmp = std::string("imafd") + (p+1);
80 p = &tmp[0];
81 } else if (*p != 'i') {
82 bad_isa_string(str);
83 }
84
85 isa_string = "rv" + std::to_string(max_xlen) + p;
86 isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
87 isa |= 1L << ('u' - 'a'); // advertise support for user mode
88
89 while (*p) {
90 isa |= 1L << (*p - 'a');
91
92 if (auto next = strchr(all_subsets, *p)) {
93 all_subsets = next + 1;
94 p++;
95 } else if (*p == 'x') {
96 const char* ext = p+1, *end = ext;
97 while (islower(*end))
98 end++;
99 register_extension(find_extension(std::string(ext, end - ext).c_str())());
100 p = end;
101 } else {
102 bad_isa_string(str);
103 }
104 }
105
106 if (supports_extension('D') && !supports_extension('F'))
107 bad_isa_string(str);
108
109 // advertise support for supervisor and user modes
110 isa |= 1L << ('s' - 'a');
111 isa |= 1L << ('u' - 'a');
112
113 max_isa = isa;
114 }
115
116 void state_t::reset()
117 {
118 memset(this, 0, sizeof(*this));
119 prv = PRV_M;
120 pc = DEFAULT_RSTVEC;
121 mtvec = DEFAULT_MTVEC;
122 load_reservation = -1;
123 tselect = 0;
124 for (unsigned int i = 0; i < num_triggers; i++)
125 mcontrol[i].type = 2;
126 }
127
128 void processor_t::set_debug(bool value)
129 {
130 debug = value;
131 if (ext)
132 ext->set_debug(value);
133 }
134
135 void processor_t::set_histogram(bool value)
136 {
137 histogram_enabled = value;
138 #ifndef RISCV_ENABLE_HISTOGRAM
139 if (value) {
140 fprintf(stderr, "PC Histogram support has not been properly enabled;");
141 fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
142 }
143 #endif
144 }
145
146 void processor_t::reset()
147 {
148 state.reset();
149 state.dcsr.halt = halt_on_reset;
150 halt_on_reset = false;
151 set_csr(CSR_MSTATUS, state.mstatus);
152
153 if (ext)
154 ext->reset(); // reset the extension
155 }
156
157 void processor_t::raise_interrupt(reg_t which)
158 {
159 throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
160 }
161
162 // Count number of contiguous 0 bits starting from the LSB.
163 static int ctz(reg_t val)
164 {
165 int res = 0;
166 if (val)
167 while ((val & 1) == 0)
168 val >>= 1, res++;
169 return res;
170 }
171
172 void processor_t::take_interrupt()
173 {
174 reg_t pending_interrupts = state.mip & state.mie;
175
176 reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
177 reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
178 reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
179
180 reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
181 reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
182 enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
183
184 if (enabled_interrupts)
185 raise_interrupt(ctz(enabled_interrupts));
186 }
187
188 void processor_t::set_privilege(reg_t prv)
189 {
190 assert(prv <= PRV_M);
191 if (prv == PRV_H)
192 prv = PRV_U;
193 mmu->flush_tlb();
194 state.prv = prv;
195 }
196
197 void processor_t::enter_debug_mode(uint8_t cause)
198 {
199 state.dcsr.cause = cause;
200 state.dcsr.prv = state.prv;
201 set_privilege(PRV_M);
202 state.dpc = state.pc;
203 state.pc = debug_rom_entry();
204 }
205
206 void processor_t::take_trap(trap_t& t, reg_t epc)
207 {
208 if (debug) {
209 fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
210 id, t.name(), epc);
211 if (t.has_badaddr())
212 fprintf(stderr, "core %3d: badaddr 0x%016" PRIx64 "\n", id,
213 t.get_badaddr());
214 }
215
216 if (state.dcsr.cause) {
217 if (t.cause() == CAUSE_BREAKPOINT) {
218 state.pc = debug_rom_entry();
219 } else {
220 state.pc = DEBUG_ROM_EXCEPTION;
221 }
222 return;
223 }
224
225 if (t.cause() == CAUSE_BREAKPOINT && (
226 (state.prv == PRV_M && state.dcsr.ebreakm) ||
227 (state.prv == PRV_H && state.dcsr.ebreakh) ||
228 (state.prv == PRV_S && state.dcsr.ebreaks) ||
229 (state.prv == PRV_U && state.dcsr.ebreaku))) {
230 enter_debug_mode(DCSR_CAUSE_SWBP);
231 return;
232 }
233
234 // by default, trap to M-mode, unless delegated to S-mode
235 reg_t bit = t.cause();
236 reg_t deleg = state.medeleg;
237 if (bit & ((reg_t)1 << (max_xlen-1)))
238 deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
239 if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
240 // handle the trap in S-mode
241 state.pc = state.stvec;
242 state.scause = t.cause();
243 state.sepc = epc;
244 if (t.has_badaddr())
245 state.sbadaddr = t.get_badaddr();
246
247 reg_t s = state.mstatus;
248 s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
249 s = set_field(s, MSTATUS_SPP, state.prv);
250 s = set_field(s, MSTATUS_SIE, 0);
251 set_csr(CSR_MSTATUS, s);
252 set_privilege(PRV_S);
253 } else {
254 state.pc = state.mtvec;
255 state.mepc = epc;
256 state.mcause = t.cause();
257 if (t.has_badaddr())
258 state.mbadaddr = t.get_badaddr();
259
260 reg_t s = state.mstatus;
261 s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
262 s = set_field(s, MSTATUS_MPP, state.prv);
263 s = set_field(s, MSTATUS_MIE, 0);
264 set_csr(CSR_MSTATUS, s);
265 set_privilege(PRV_M);
266 }
267
268 yield_load_reservation();
269 }
270
271 void processor_t::disasm(insn_t insn)
272 {
273 uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
274 fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
275 id, state.pc, bits, disassembler->disassemble(insn).c_str());
276 }
277
278 static bool validate_vm(int max_xlen, reg_t vm)
279 {
280 if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
281 return true;
282 if (max_xlen == 32 && vm == VM_SV32)
283 return true;
284 return vm == VM_MBARE;
285 }
286
287 int processor_t::paddr_bits()
288 {
289 assert(xlen == max_xlen);
290 return max_xlen == 64 ? 50 : 34;
291 }
292
293 void processor_t::set_csr(int which, reg_t val)
294 {
295 val = zext_xlen(val);
296 reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
297 reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
298 switch (which)
299 {
300 case CSR_FFLAGS:
301 dirty_fp_state;
302 state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
303 break;
304 case CSR_FRM:
305 dirty_fp_state;
306 state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
307 break;
308 case CSR_FCSR:
309 dirty_fp_state;
310 state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
311 state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
312 break;
313 case CSR_MSTATUS: {
314 if ((val ^ state.mstatus) &
315 (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM | MSTATUS_MXR))
316 mmu->flush_tlb();
317
318 reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
319 | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
320 | MSTATUS_MPP | MSTATUS_MXR | (ext ? MSTATUS_XS : 0);
321
322 if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
323 mask |= MSTATUS_VM;
324
325 state.mstatus = (state.mstatus & ~mask) | (val & mask);
326
327 bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
328 dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
329 if (max_xlen == 32)
330 state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
331 else
332 state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
333
334 // spike supports the notion of xlen < max_xlen, but current priv spec
335 // doesn't provide a mechanism to run RV32 software on an RV64 machine
336 xlen = max_xlen;
337 break;
338 }
339 case CSR_MIP: {
340 reg_t mask = MIP_SSIP | MIP_STIP;
341 state.mip = (state.mip & ~mask) | (val & mask);
342 break;
343 }
344 case CSR_MIE:
345 state.mie = (state.mie & ~all_ints) | (val & all_ints);
346 break;
347 case CSR_MIDELEG:
348 state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
349 break;
350 case CSR_MEDELEG: {
351 reg_t mask = 0;
352 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
353 #include "encoding.h"
354 #undef DECLARE_CAUSE
355 state.medeleg = (state.medeleg & ~mask) | (val & mask);
356 break;
357 }
358 case CSR_MINSTRET:
359 case CSR_MCYCLE:
360 if (xlen == 32)
361 state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
362 else
363 state.minstret = val;
364 break;
365 case CSR_MINSTRETH:
366 case CSR_MCYCLEH:
367 state.minstret = (val << 32) | (state.minstret << 32 >> 32);
368 break;
369 case CSR_MUCOUNTEREN:
370 state.mucounteren = val;
371 break;
372 case CSR_MSCOUNTEREN:
373 state.mscounteren = val;
374 break;
375 case CSR_SSTATUS: {
376 reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
377 | SSTATUS_XS | SSTATUS_PUM;
378 return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
379 }
380 case CSR_SIP: {
381 reg_t mask = MIP_SSIP & state.mideleg;
382 return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
383 }
384 case CSR_SIE:
385 return set_csr(CSR_MIE,
386 (state.mie & ~state.mideleg) | (val & state.mideleg));
387 case CSR_SPTBR: {
388 // upper bits of sptbr are the ASID; we only support ASID = 0
389 state.sptbr = val & (((reg_t)1 << (paddr_bits() - PGSHIFT)) - 1);
390 break;
391 }
392 case CSR_SEPC: state.sepc = val; break;
393 case CSR_STVEC: state.stvec = val >> 2 << 2; break;
394 case CSR_SSCRATCH: state.sscratch = val; break;
395 case CSR_SCAUSE: state.scause = val; break;
396 case CSR_SBADADDR: state.sbadaddr = val; break;
397 case CSR_MEPC: state.mepc = val; break;
398 case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
399 case CSR_MSCRATCH: state.mscratch = val; break;
400 case CSR_MCAUSE: state.mcause = val; break;
401 case CSR_MBADADDR: state.mbadaddr = val; break;
402 case CSR_MISA: {
403 if (!(val & (1L << ('F' - 'A'))))
404 val &= ~(1L << ('D' - 'A'));
405
406 // allow MAFDC bits in MISA to be modified
407 reg_t mask = 0;
408 mask |= 1L << ('M' - 'A');
409 mask |= 1L << ('A' - 'A');
410 mask |= 1L << ('F' - 'A');
411 mask |= 1L << ('D' - 'A');
412 mask |= 1L << ('C' - 'A');
413 mask &= max_isa;
414
415 isa = (val & mask) | (isa & ~mask);
416 break;
417 }
418 case CSR_TSELECT:
419 if (val < state.num_triggers) {
420 state.tselect = val;
421 }
422 break;
423 case CSR_TDATA1:
424 {
425 mcontrol_t *mc = &state.mcontrol[state.tselect];
426 if (mc->dmode && !state.dcsr.cause) {
427 break;
428 }
429 mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
430 mc->select = get_field(val, MCONTROL_SELECT);
431 mc->timing = get_field(val, MCONTROL_TIMING);
432 mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
433 mc->chain = get_field(val, MCONTROL_CHAIN);
434 mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
435 mc->m = get_field(val, MCONTROL_M);
436 mc->h = get_field(val, MCONTROL_H);
437 mc->s = get_field(val, MCONTROL_S);
438 mc->u = get_field(val, MCONTROL_U);
439 mc->execute = get_field(val, MCONTROL_EXECUTE);
440 mc->store = get_field(val, MCONTROL_STORE);
441 mc->load = get_field(val, MCONTROL_LOAD);
442 // Assume we're here because of csrw.
443 if (mc->execute)
444 mc->timing = 0;
445 trigger_updated();
446 }
447 break;
448 case CSR_TDATA2:
449 if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
450 break;
451 }
452 if (state.tselect < state.num_triggers) {
453 state.tdata2[state.tselect] = val;
454 }
455 break;
456 case CSR_DCSR:
457 state.dcsr.prv = get_field(val, DCSR_PRV);
458 state.dcsr.step = get_field(val, DCSR_STEP);
459 // TODO: ndreset and fullreset
460 state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
461 state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
462 state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
463 state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
464 state.dcsr.halt = get_field(val, DCSR_HALT);
465 break;
466 case CSR_DPC:
467 state.dpc = val;
468 break;
469 case CSR_DSCRATCH:
470 state.dscratch = val;
471 break;
472 }
473 }
474
475 reg_t processor_t::get_csr(int which)
476 {
477 reg_t ctr_en = state.prv == PRV_U ? state.mucounteren :
478 state.prv == PRV_S ? state.mscounteren : -1U;
479 bool ctr_ok = (ctr_en >> (which & 31)) & 1;
480
481 if (ctr_ok) {
482 if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
483 return 0;
484 if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
485 return 0;
486 }
487 if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
488 return 0;
489 if (xlen == 32 && which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
490 return 0;
491 if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
492 return 0;
493
494 switch (which)
495 {
496 case CSR_FFLAGS:
497 require_fp;
498 if (!supports_extension('F'))
499 break;
500 return state.fflags;
501 case CSR_FRM:
502 require_fp;
503 if (!supports_extension('F'))
504 break;
505 return state.frm;
506 case CSR_FCSR:
507 require_fp;
508 if (!supports_extension('F'))
509 break;
510 return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
511 case CSR_INSTRET:
512 case CSR_CYCLE:
513 if (ctr_ok)
514 return state.minstret;
515 break;
516 case CSR_MINSTRET:
517 case CSR_MCYCLE:
518 return state.minstret;
519 case CSR_MINSTRETH:
520 case CSR_MCYCLEH:
521 if (xlen == 32)
522 return state.minstret >> 32;
523 break;
524 case CSR_MUCOUNTEREN: return state.mucounteren;
525 case CSR_MSCOUNTEREN: return state.mscounteren;
526 case CSR_SSTATUS: {
527 reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
528 | SSTATUS_XS | SSTATUS_PUM;
529 reg_t sstatus = state.mstatus & mask;
530 if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
531 (sstatus & SSTATUS_XS) == SSTATUS_XS)
532 sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
533 return sstatus;
534 }
535 case CSR_SIP: return state.mip & state.mideleg;
536 case CSR_SIE: return state.mie & state.mideleg;
537 case CSR_SEPC: return state.sepc;
538 case CSR_SBADADDR: return state.sbadaddr;
539 case CSR_STVEC: return state.stvec;
540 case CSR_SCAUSE:
541 if (max_xlen > xlen)
542 return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
543 return state.scause;
544 case CSR_SPTBR: return state.sptbr;
545 case CSR_SSCRATCH: return state.sscratch;
546 case CSR_MSTATUS: return state.mstatus;
547 case CSR_MIP: return state.mip;
548 case CSR_MIE: return state.mie;
549 case CSR_MEPC: return state.mepc;
550 case CSR_MSCRATCH: return state.mscratch;
551 case CSR_MCAUSE: return state.mcause;
552 case CSR_MBADADDR: return state.mbadaddr;
553 case CSR_MISA: return isa;
554 case CSR_MARCHID: return 0;
555 case CSR_MIMPID: return 0;
556 case CSR_MVENDORID: return 0;
557 case CSR_MHARTID: return id;
558 case CSR_MTVEC: return state.mtvec;
559 case CSR_MEDELEG: return state.medeleg;
560 case CSR_MIDELEG: return state.mideleg;
561 case CSR_TSELECT: return state.tselect;
562 case CSR_TDATA1:
563 if (state.tselect < state.num_triggers) {
564 reg_t v = 0;
565 mcontrol_t *mc = &state.mcontrol[state.tselect];
566 v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
567 v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
568 v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
569 v = set_field(v, MCONTROL_SELECT, mc->select);
570 v = set_field(v, MCONTROL_TIMING, mc->timing);
571 v = set_field(v, MCONTROL_ACTION, mc->action);
572 v = set_field(v, MCONTROL_CHAIN, mc->chain);
573 v = set_field(v, MCONTROL_MATCH, mc->match);
574 v = set_field(v, MCONTROL_M, mc->m);
575 v = set_field(v, MCONTROL_H, mc->h);
576 v = set_field(v, MCONTROL_S, mc->s);
577 v = set_field(v, MCONTROL_U, mc->u);
578 v = set_field(v, MCONTROL_EXECUTE, mc->execute);
579 v = set_field(v, MCONTROL_STORE, mc->store);
580 v = set_field(v, MCONTROL_LOAD, mc->load);
581 return v;
582 } else {
583 return 0;
584 }
585 break;
586 case CSR_TDATA2:
587 if (state.tselect < state.num_triggers) {
588 return state.tdata2[state.tselect];
589 } else {
590 return 0;
591 }
592 break;
593 case CSR_TDATA3: return 0;
594 case CSR_DCSR:
595 {
596 uint32_t v = 0;
597 v = set_field(v, DCSR_XDEBUGVER, 1);
598 v = set_field(v, DCSR_NDRESET, 0);
599 v = set_field(v, DCSR_FULLRESET, 0);
600 v = set_field(v, DCSR_PRV, state.dcsr.prv);
601 v = set_field(v, DCSR_STEP, state.dcsr.step);
602 v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
603 v = set_field(v, DCSR_STOPCYCLE, 0);
604 v = set_field(v, DCSR_STOPTIME, 0);
605 v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
606 v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
607 v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
608 v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
609 v = set_field(v, DCSR_HALT, state.dcsr.halt);
610 v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
611 return v;
612 }
613 case CSR_DPC:
614 return state.dpc;
615 case CSR_DSCRATCH:
616 return state.dscratch;
617 }
618 throw trap_illegal_instruction();
619 }
620
621 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
622 {
623 throw trap_illegal_instruction();
624 }
625
626 insn_func_t processor_t::decode_insn(insn_t insn)
627 {
628 // look up opcode in hash table
629 size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
630 insn_desc_t desc = opcode_cache[idx];
631
632 if (unlikely(insn.bits() != desc.match)) {
633 // fall back to linear search
634 insn_desc_t* p = &instructions[0];
635 while ((insn.bits() & p->mask) != p->match)
636 p++;
637 desc = *p;
638
639 if (p->mask != 0 && p > &instructions[0]) {
640 if (p->match != (p-1)->match && p->match != (p+1)->match) {
641 // move to front of opcode list to reduce miss penalty
642 while (--p >= &instructions[0])
643 *(p+1) = *p;
644 instructions[0] = desc;
645 }
646 }
647
648 opcode_cache[idx] = desc;
649 opcode_cache[idx].match = insn.bits();
650 }
651
652 return xlen == 64 ? desc.rv64 : desc.rv32;
653 }
654
655 void processor_t::register_insn(insn_desc_t desc)
656 {
657 instructions.push_back(desc);
658 }
659
660 void processor_t::build_opcode_map()
661 {
662 struct cmp {
663 bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
664 if (lhs.match == rhs.match)
665 return lhs.mask > rhs.mask;
666 return lhs.match > rhs.match;
667 }
668 };
669 std::sort(instructions.begin(), instructions.end(), cmp());
670
671 for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
672 opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
673 }
674
675 void processor_t::register_extension(extension_t* x)
676 {
677 for (auto insn : x->get_instructions())
678 register_insn(insn);
679 build_opcode_map();
680 for (auto disasm_insn : x->get_disasms())
681 disassembler->add_insn(disasm_insn);
682 if (ext != NULL)
683 throw std::logic_error("only one extension may be registered");
684 ext = x;
685 x->set_processor(this);
686 }
687
688 void processor_t::register_base_instructions()
689 {
690 #define DECLARE_INSN(name, match, mask) \
691 insn_bits_t name##_match = (match), name##_mask = (mask);
692 #include "encoding.h"
693 #undef DECLARE_INSN
694
695 #define DEFINE_INSN(name) \
696 REGISTER_INSN(this, name, name##_match, name##_mask)
697 #include "insn_list.h"
698 #undef DEFINE_INSN
699
700 register_insn({0, 0, &illegal_instruction, &illegal_instruction});
701 build_opcode_map();
702 }
703
704 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
705 {
706 return false;
707 }
708
709 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
710 {
711 switch (addr)
712 {
713 case 0:
714 state.mip &= ~MIP_MSIP;
715 if (bytes[0] & 1)
716 state.mip |= MIP_MSIP;
717 return true;
718
719 default:
720 return false;
721 }
722 }
723
724 void processor_t::trigger_updated()
725 {
726 mmu->flush_tlb();
727 mmu->check_triggers_fetch = false;
728 mmu->check_triggers_load = false;
729 mmu->check_triggers_store = false;
730
731 for (unsigned i = 0; i < state.num_triggers; i++) {
732 if (state.mcontrol[i].execute) {
733 mmu->check_triggers_fetch = true;
734 }
735 if (state.mcontrol[i].load) {
736 mmu->check_triggers_load = true;
737 }
738 if (state.mcontrol[i].store) {
739 mmu->check_triggers_store = true;
740 }
741 }
742 }