1 // See LICENSE for license details.
22 processor_t::processor_t(const char* isa
, simif_t
* sim
, uint32_t id
,
24 : debug(false), halt_request(false), sim(sim
), ext(NULL
), id(id
),
25 halt_on_reset(halt_on_reset
), last_pc(1), executions(1)
27 parse_isa_string(isa
);
28 register_base_instructions();
30 mmu
= new mmu_t(sim
, this);
32 disassembler
= new disassembler_t(max_xlen
);
34 for (auto disasm_insn
: ext
->get_disasms())
35 disassembler
->add_insn(disasm_insn
);
40 processor_t::~processor_t()
42 #ifdef RISCV_ENABLE_HISTOGRAM
43 if (histogram_enabled
)
45 fprintf(stderr
, "PC Histogram size:%zu\n", pc_histogram
.size());
46 for (auto it
: pc_histogram
)
47 fprintf(stderr
, "%0" PRIx64
" %" PRIu64
"\n", it
.first
, it
.second
);
55 static void bad_isa_string(const char* isa
)
57 fprintf(stderr
, "error: bad --isa option %s\n", isa
);
61 void processor_t::parse_isa_string(const char* str
)
63 std::string lowercase
, tmp
;
64 for (const char *r
= str
; *r
; r
++)
65 lowercase
+= std::tolower(*r
);
67 const char* p
= lowercase
.c_str();
68 const char* all_subsets
= "imafdqc";
71 state
.misa
= reg_t(2) << 62;
73 if (strncmp(p
, "rv32", 4) == 0)
74 max_xlen
= 32, state
.misa
= reg_t(1) << 30, p
+= 4;
75 else if (strncmp(p
, "rv64", 4) == 0)
77 else if (strncmp(p
, "rv", 2) == 0)
82 } else if (*p
== 'g') { // treat "G" as "IMAFD"
83 tmp
= std::string("imafd") + (p
+1);
85 } else if (*p
!= 'i') {
89 isa_string
= "rv" + std::to_string(max_xlen
) + p
;
90 state
.misa
|= 1L << ('s' - 'a'); // advertise support for supervisor mode
91 state
.misa
|= 1L << ('u' - 'a'); // advertise support for user mode
94 state
.misa
|= 1L << (*p
- 'a');
96 if (auto next
= strchr(all_subsets
, *p
)) {
97 all_subsets
= next
+ 1;
99 } else if (*p
== 'x') {
100 const char* ext
= p
+1, *end
= ext
;
101 while (islower(*end
))
103 register_extension(find_extension(std::string(ext
, end
- ext
).c_str())());
110 if (supports_extension('D') && !supports_extension('F'))
113 if (supports_extension('Q') && !supports_extension('D'))
116 if (supports_extension('Q') && max_xlen
< 64)
119 max_isa
= state
.misa
;
122 void state_t::reset(reg_t max_isa
)
124 memset(this, 0, sizeof(*this));
129 for (unsigned int i
= 0; i
< num_triggers
; i
++)
130 mcontrol
[i
].type
= 2;
133 void processor_t::set_debug(bool value
)
137 ext
->set_debug(value
);
140 void processor_t::set_histogram(bool value
)
142 histogram_enabled
= value
;
143 #ifndef RISCV_ENABLE_HISTOGRAM
145 fprintf(stderr
, "PC Histogram support has not been properly enabled;");
146 fprintf(stderr
, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
151 void processor_t::reset()
153 state
.reset(max_isa
);
154 state
.dcsr
.halt
= halt_on_reset
;
155 halt_on_reset
= false;
156 set_csr(CSR_MSTATUS
, state
.mstatus
);
159 ext
->reset(); // reset the extension
165 // Count number of contiguous 0 bits starting from the LSB.
166 static int ctz(reg_t val
)
170 while ((val
& 1) == 0)
175 void processor_t::take_interrupt(reg_t pending_interrupts
)
177 reg_t mie
= get_field(state
.mstatus
, MSTATUS_MIE
);
178 reg_t m_enabled
= state
.prv
< PRV_M
|| (state
.prv
== PRV_M
&& mie
);
179 reg_t enabled_interrupts
= pending_interrupts
& ~state
.mideleg
& -m_enabled
;
181 reg_t sie
= get_field(state
.mstatus
, MSTATUS_SIE
);
182 reg_t s_enabled
= state
.prv
< PRV_S
|| (state
.prv
== PRV_S
&& sie
);
183 // M-ints have highest priority; consider S-ints only if no M-ints pending
184 if (enabled_interrupts
== 0)
185 enabled_interrupts
= pending_interrupts
& state
.mideleg
& -s_enabled
;
187 if (state
.dcsr
.cause
== 0 && enabled_interrupts
) {
188 // nonstandard interrupts have highest priority
189 if (enabled_interrupts
>> IRQ_M_EXT
)
190 enabled_interrupts
= enabled_interrupts
>> IRQ_M_EXT
<< IRQ_M_EXT
;
191 // external interrupts have next-highest priority
192 else if (enabled_interrupts
& (MIP_MEIP
| MIP_SEIP
))
193 enabled_interrupts
= enabled_interrupts
& (MIP_MEIP
| MIP_SEIP
);
194 // software interrupts have next-highest priority
195 else if (enabled_interrupts
& (MIP_MSIP
| MIP_SSIP
))
196 enabled_interrupts
= enabled_interrupts
& (MIP_MSIP
| MIP_SSIP
);
197 // timer interrupts have next-highest priority
198 else if (enabled_interrupts
& (MIP_MTIP
| MIP_STIP
))
199 enabled_interrupts
= enabled_interrupts
& (MIP_MTIP
| MIP_STIP
);
203 throw trap_t(((reg_t
)1 << (max_xlen
-1)) | ctz(enabled_interrupts
));
207 static int xlen_to_uxl(int xlen
)
216 reg_t
processor_t::legalize_privilege(reg_t prv
)
218 assert(prv
<= PRV_M
);
220 if (!supports_extension('U'))
223 if (prv
== PRV_H
|| !supports_extension('S'))
229 void processor_t::set_privilege(reg_t prv
)
232 state
.prv
= legalize_privilege(prv
);
235 void processor_t::enter_debug_mode(uint8_t cause
)
237 state
.dcsr
.cause
= cause
;
238 state
.dcsr
.prv
= state
.prv
;
239 set_privilege(PRV_M
);
240 state
.dpc
= state
.pc
;
241 state
.pc
= DEBUG_ROM_ENTRY
;
244 void processor_t::take_trap(trap_t
& t
, reg_t epc
)
247 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
250 fprintf(stderr
, "core %3d: tval 0x%016" PRIx64
"\n", id
,
254 if (state
.dcsr
.cause
) {
255 if (t
.cause() == CAUSE_BREAKPOINT
) {
256 state
.pc
= DEBUG_ROM_ENTRY
;
258 state
.pc
= DEBUG_ROM_TVEC
;
263 if (t
.cause() == CAUSE_BREAKPOINT
&& (
264 (state
.prv
== PRV_M
&& state
.dcsr
.ebreakm
) ||
265 (state
.prv
== PRV_S
&& state
.dcsr
.ebreaks
) ||
266 (state
.prv
== PRV_U
&& state
.dcsr
.ebreaku
))) {
267 enter_debug_mode(DCSR_CAUSE_SWBP
);
271 // by default, trap to M-mode, unless delegated to S-mode
272 reg_t bit
= t
.cause();
273 reg_t deleg
= state
.medeleg
;
274 bool interrupt
= (bit
& ((reg_t
)1 << (max_xlen
-1))) != 0;
276 deleg
= state
.mideleg
, bit
&= ~((reg_t
)1 << (max_xlen
-1));
277 if (state
.prv
<= PRV_S
&& bit
< max_xlen
&& ((deleg
>> bit
) & 1)) {
278 // handle the trap in S-mode
279 state
.pc
= state
.stvec
;
280 state
.scause
= t
.cause();
282 state
.stval
= t
.get_tval();
284 reg_t s
= state
.mstatus
;
285 s
= set_field(s
, MSTATUS_SPIE
, get_field(s
, MSTATUS_SIE
));
286 s
= set_field(s
, MSTATUS_SPP
, state
.prv
);
287 s
= set_field(s
, MSTATUS_SIE
, 0);
288 set_csr(CSR_MSTATUS
, s
);
289 set_privilege(PRV_S
);
291 reg_t vector
= (state
.mtvec
& 1) && interrupt
? 4*bit
: 0;
292 state
.pc
= (state
.mtvec
& ~(reg_t
)1) + vector
;
294 state
.mcause
= t
.cause();
295 state
.mtval
= t
.get_tval();
297 reg_t s
= state
.mstatus
;
298 s
= set_field(s
, MSTATUS_MPIE
, get_field(s
, MSTATUS_MIE
));
299 s
= set_field(s
, MSTATUS_MPP
, state
.prv
);
300 s
= set_field(s
, MSTATUS_MIE
, 0);
301 set_csr(CSR_MSTATUS
, s
);
302 set_privilege(PRV_M
);
306 void processor_t::disasm(insn_t insn
)
308 uint64_t bits
= insn
.bits() & ((1ULL << (8 * insn_length(insn
.bits()))) - 1);
309 if (last_pc
!= state
.pc
|| last_bits
!= bits
) {
310 if (executions
!= 1) {
311 fprintf(stderr
, "core %3d: Executed %" PRIx64
" times\n", id
, executions
);
314 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx64
") %s\n",
315 id
, state
.pc
, bits
, disassembler
->disassemble(insn
).c_str());
324 int processor_t::paddr_bits()
326 assert(xlen
== max_xlen
);
327 return max_xlen
== 64 ? 50 : 34;
330 void processor_t::set_csr(int which
, reg_t val
)
332 val
= zext_xlen(val
);
333 reg_t delegable_ints
= MIP_SSIP
| MIP_STIP
| MIP_SEIP
334 | ((ext
!= NULL
) << IRQ_COP
);
335 reg_t all_ints
= delegable_ints
| MIP_MSIP
| MIP_MTIP
;
340 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
344 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
348 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
349 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
352 if ((val
^ state
.mstatus
) &
353 (MSTATUS_MPP
| MSTATUS_MPRV
| MSTATUS_SUM
| MSTATUS_MXR
))
356 reg_t mask
= MSTATUS_SIE
| MSTATUS_SPIE
| MSTATUS_MIE
| MSTATUS_MPIE
357 | MSTATUS_FS
| MSTATUS_MPRV
| MSTATUS_SUM
358 | MSTATUS_MXR
| MSTATUS_TW
| MSTATUS_TVM
359 | MSTATUS_TSR
| MSTATUS_UXL
| MSTATUS_SXL
|
360 (ext
? MSTATUS_XS
: 0);
362 reg_t requested_mpp
= legalize_privilege(get_field(val
, MSTATUS_MPP
));
363 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_MPP
, requested_mpp
);
364 if (supports_extension('S'))
367 state
.mstatus
= (state
.mstatus
& ~mask
) | (val
& mask
);
369 bool dirty
= (state
.mstatus
& MSTATUS_FS
) == MSTATUS_FS
;
370 dirty
|= (state
.mstatus
& MSTATUS_XS
) == MSTATUS_XS
;
372 state
.mstatus
= set_field(state
.mstatus
, MSTATUS32_SD
, dirty
);
374 state
.mstatus
= set_field(state
.mstatus
, MSTATUS64_SD
, dirty
);
376 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_UXL
, xlen_to_uxl(max_xlen
));
377 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_UXL
, xlen_to_uxl(max_xlen
));
378 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_SXL
, xlen_to_uxl(max_xlen
));
379 // U-XLEN == S-XLEN == M-XLEN
384 reg_t mask
= MIP_SSIP
| MIP_STIP
;
385 state
.mip
= (state
.mip
& ~mask
) | (val
& mask
);
389 state
.mie
= (state
.mie
& ~all_ints
) | (val
& all_ints
);
392 state
.mideleg
= (state
.mideleg
& ~delegable_ints
) | (val
& delegable_ints
);
396 (1 << CAUSE_MISALIGNED_FETCH
) |
397 (1 << CAUSE_BREAKPOINT
) |
398 (1 << CAUSE_USER_ECALL
) |
399 (1 << CAUSE_FETCH_PAGE_FAULT
) |
400 (1 << CAUSE_LOAD_PAGE_FAULT
) |
401 (1 << CAUSE_STORE_PAGE_FAULT
);
402 state
.medeleg
= (state
.medeleg
& ~mask
) | (val
& mask
);
408 state
.minstret
= (state
.minstret
>> 32 << 32) | (val
& 0xffffffffU
);
410 state
.minstret
= val
;
411 // The ISA mandates that if an instruction writes instret, the write
412 // takes precedence over the increment to instret. However, Spike
413 // unconditionally increments instret after executing an instruction.
414 // Correct for this artifact by decrementing instret here.
419 state
.minstret
= (val
<< 32) | (state
.minstret
<< 32 >> 32);
420 state
.minstret
--; // See comment above.
423 state
.scounteren
= val
;
426 state
.mcounteren
= val
;
429 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
430 | SSTATUS_XS
| SSTATUS_SUM
| SSTATUS_MXR
;
431 return set_csr(CSR_MSTATUS
, (state
.mstatus
& ~mask
) | (val
& mask
));
434 reg_t mask
= MIP_SSIP
& state
.mideleg
;
435 return set_csr(CSR_MIP
, (state
.mip
& ~mask
) | (val
& mask
));
438 return set_csr(CSR_MIE
,
439 (state
.mie
& ~state
.mideleg
) | (val
& state
.mideleg
));
443 state
.satp
= val
& (SATP32_PPN
| SATP32_MODE
);
444 if (max_xlen
== 64 && (get_field(val
, SATP64_MODE
) == SATP_MODE_OFF
||
445 get_field(val
, SATP64_MODE
) == SATP_MODE_SV39
||
446 get_field(val
, SATP64_MODE
) == SATP_MODE_SV48
))
447 state
.satp
= val
& (SATP64_PPN
| SATP64_MODE
);
450 case CSR_SEPC
: state
.sepc
= val
& ~(reg_t
)1; break;
451 case CSR_STVEC
: state
.stvec
= val
>> 2 << 2; break;
452 case CSR_SSCRATCH
: state
.sscratch
= val
; break;
453 case CSR_SCAUSE
: state
.scause
= val
; break;
454 case CSR_STVAL
: state
.stval
= val
; break;
455 case CSR_MEPC
: state
.mepc
= val
& ~(reg_t
)1; break;
456 case CSR_MTVEC
: state
.mtvec
= val
& ~(reg_t
)2; break;
457 case CSR_MSCRATCH
: state
.mscratch
= val
; break;
458 case CSR_MCAUSE
: state
.mcause
= val
; break;
459 case CSR_MTVAL
: state
.mtval
= val
; break;
461 // the write is ignored if increasing IALIGN would misalign the PC
462 if (!(val
& (1L << ('C' - 'A'))) && (state
.pc
& 2))
465 if (!(val
& (1L << ('F' - 'A'))))
466 val
&= ~(1L << ('D' - 'A'));
468 // allow MAFDC bits in MISA to be modified
470 mask
|= 1L << ('M' - 'A');
471 mask
|= 1L << ('A' - 'A');
472 mask
|= 1L << ('F' - 'A');
473 mask
|= 1L << ('D' - 'A');
474 mask
|= 1L << ('C' - 'A');
477 state
.misa
= (val
& mask
) | (state
.misa
& ~mask
);
481 if (val
< state
.num_triggers
) {
487 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
488 if (mc
->dmode
&& !state
.dcsr
.cause
) {
491 mc
->dmode
= get_field(val
, MCONTROL_DMODE(xlen
));
492 mc
->select
= get_field(val
, MCONTROL_SELECT
);
493 mc
->timing
= get_field(val
, MCONTROL_TIMING
);
494 mc
->action
= (mcontrol_action_t
) get_field(val
, MCONTROL_ACTION
);
495 mc
->chain
= get_field(val
, MCONTROL_CHAIN
);
496 mc
->match
= (mcontrol_match_t
) get_field(val
, MCONTROL_MATCH
);
497 mc
->m
= get_field(val
, MCONTROL_M
);
498 mc
->h
= get_field(val
, MCONTROL_H
);
499 mc
->s
= get_field(val
, MCONTROL_S
);
500 mc
->u
= get_field(val
, MCONTROL_U
);
501 mc
->execute
= get_field(val
, MCONTROL_EXECUTE
);
502 mc
->store
= get_field(val
, MCONTROL_STORE
);
503 mc
->load
= get_field(val
, MCONTROL_LOAD
);
504 // Assume we're here because of csrw.
511 if (state
.mcontrol
[state
.tselect
].dmode
&& !state
.dcsr
.cause
) {
514 if (state
.tselect
< state
.num_triggers
) {
515 state
.tdata2
[state
.tselect
] = val
;
519 state
.dcsr
.prv
= get_field(val
, DCSR_PRV
);
520 state
.dcsr
.step
= get_field(val
, DCSR_STEP
);
521 // TODO: ndreset and fullreset
522 state
.dcsr
.ebreakm
= get_field(val
, DCSR_EBREAKM
);
523 state
.dcsr
.ebreakh
= get_field(val
, DCSR_EBREAKH
);
524 state
.dcsr
.ebreaks
= get_field(val
, DCSR_EBREAKS
);
525 state
.dcsr
.ebreaku
= get_field(val
, DCSR_EBREAKU
);
526 state
.dcsr
.halt
= get_field(val
, DCSR_HALT
);
529 state
.dpc
= val
& ~(reg_t
)1;
532 state
.dscratch
= val
;
537 reg_t
processor_t::get_csr(int which
)
539 uint32_t ctr_en
= -1;
540 if (state
.prv
< PRV_M
)
541 ctr_en
&= state
.mcounteren
;
542 if (state
.prv
< PRV_S
)
543 ctr_en
&= state
.scounteren
;
544 bool ctr_ok
= (ctr_en
>> (which
& 31)) & 1;
547 if (which
>= CSR_HPMCOUNTER3
&& which
<= CSR_HPMCOUNTER31
)
549 if (xlen
== 32 && which
>= CSR_HPMCOUNTER3H
&& which
<= CSR_HPMCOUNTER31H
)
552 if (which
>= CSR_MHPMCOUNTER3
&& which
<= CSR_MHPMCOUNTER31
)
554 if (xlen
== 32 && which
>= CSR_MHPMCOUNTER3H
&& which
<= CSR_MHPMCOUNTER31H
)
556 if (which
>= CSR_MHPMEVENT3
&& which
<= CSR_MHPMEVENT31
)
563 if (!supports_extension('F'))
568 if (!supports_extension('F'))
573 if (!supports_extension('F'))
575 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
579 return state
.minstret
;
583 return state
.minstret
;
586 if (ctr_ok
&& xlen
== 32)
587 return state
.minstret
>> 32;
592 return state
.minstret
>> 32;
594 case CSR_SCOUNTEREN
: return state
.scounteren
;
595 case CSR_MCOUNTEREN
: return state
.mcounteren
;
597 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
598 | SSTATUS_XS
| SSTATUS_SUM
| SSTATUS_MXR
| SSTATUS_UXL
;
599 reg_t sstatus
= state
.mstatus
& mask
;
600 if ((sstatus
& SSTATUS_FS
) == SSTATUS_FS
||
601 (sstatus
& SSTATUS_XS
) == SSTATUS_XS
)
602 sstatus
|= (xlen
== 32 ? SSTATUS32_SD
: SSTATUS64_SD
);
605 case CSR_SIP
: return state
.mip
& state
.mideleg
;
606 case CSR_SIE
: return state
.mie
& state
.mideleg
;
607 case CSR_SEPC
: return state
.sepc
& pc_alignment_mask();
608 case CSR_STVAL
: return state
.stval
;
609 case CSR_STVEC
: return state
.stvec
;
612 return state
.scause
| ((state
.scause
>> (max_xlen
-1)) << (xlen
-1));
615 if (get_field(state
.mstatus
, MSTATUS_TVM
))
616 require_privilege(PRV_M
);
618 case CSR_SSCRATCH
: return state
.sscratch
;
619 case CSR_MSTATUS
: return state
.mstatus
;
620 case CSR_MIP
: return state
.mip
;
621 case CSR_MIE
: return state
.mie
;
622 case CSR_MEPC
: return state
.mepc
& pc_alignment_mask();
623 case CSR_MSCRATCH
: return state
.mscratch
;
624 case CSR_MCAUSE
: return state
.mcause
;
625 case CSR_MTVAL
: return state
.mtval
;
626 case CSR_MISA
: return state
.misa
;
627 case CSR_MARCHID
: return 0;
628 case CSR_MIMPID
: return 0;
629 case CSR_MVENDORID
: return 0;
630 case CSR_MHARTID
: return id
;
631 case CSR_MTVEC
: return state
.mtvec
;
632 case CSR_MEDELEG
: return state
.medeleg
;
633 case CSR_MIDELEG
: return state
.mideleg
;
634 case CSR_TSELECT
: return state
.tselect
;
636 if (state
.tselect
< state
.num_triggers
) {
638 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
639 v
= set_field(v
, MCONTROL_TYPE(xlen
), mc
->type
);
640 v
= set_field(v
, MCONTROL_DMODE(xlen
), mc
->dmode
);
641 v
= set_field(v
, MCONTROL_MASKMAX(xlen
), mc
->maskmax
);
642 v
= set_field(v
, MCONTROL_SELECT
, mc
->select
);
643 v
= set_field(v
, MCONTROL_TIMING
, mc
->timing
);
644 v
= set_field(v
, MCONTROL_ACTION
, mc
->action
);
645 v
= set_field(v
, MCONTROL_CHAIN
, mc
->chain
);
646 v
= set_field(v
, MCONTROL_MATCH
, mc
->match
);
647 v
= set_field(v
, MCONTROL_M
, mc
->m
);
648 v
= set_field(v
, MCONTROL_H
, mc
->h
);
649 v
= set_field(v
, MCONTROL_S
, mc
->s
);
650 v
= set_field(v
, MCONTROL_U
, mc
->u
);
651 v
= set_field(v
, MCONTROL_EXECUTE
, mc
->execute
);
652 v
= set_field(v
, MCONTROL_STORE
, mc
->store
);
653 v
= set_field(v
, MCONTROL_LOAD
, mc
->load
);
660 if (state
.tselect
< state
.num_triggers
) {
661 return state
.tdata2
[state
.tselect
];
666 case CSR_TDATA3
: return 0;
670 v
= set_field(v
, DCSR_XDEBUGVER
, 1);
671 v
= set_field(v
, DCSR_EBREAKM
, state
.dcsr
.ebreakm
);
672 v
= set_field(v
, DCSR_EBREAKH
, state
.dcsr
.ebreakh
);
673 v
= set_field(v
, DCSR_EBREAKS
, state
.dcsr
.ebreaks
);
674 v
= set_field(v
, DCSR_EBREAKU
, state
.dcsr
.ebreaku
);
675 v
= set_field(v
, DCSR_STOPCYCLE
, 0);
676 v
= set_field(v
, DCSR_STOPTIME
, 0);
677 v
= set_field(v
, DCSR_CAUSE
, state
.dcsr
.cause
);
678 v
= set_field(v
, DCSR_STEP
, state
.dcsr
.step
);
679 v
= set_field(v
, DCSR_PRV
, state
.dcsr
.prv
);
683 return state
.dpc
& pc_alignment_mask();
685 return state
.dscratch
;
687 throw trap_illegal_instruction(0);
690 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
692 throw trap_illegal_instruction(0);
695 insn_func_t
processor_t::decode_insn(insn_t insn
)
697 // look up opcode in hash table
698 size_t idx
= insn
.bits() % OPCODE_CACHE_SIZE
;
699 insn_desc_t desc
= opcode_cache
[idx
];
701 if (unlikely(insn
.bits() != desc
.match
)) {
702 // fall back to linear search
703 insn_desc_t
* p
= &instructions
[0];
704 while ((insn
.bits() & p
->mask
) != p
->match
)
708 if (p
->mask
!= 0 && p
> &instructions
[0]) {
709 if (p
->match
!= (p
-1)->match
&& p
->match
!= (p
+1)->match
) {
710 // move to front of opcode list to reduce miss penalty
711 while (--p
>= &instructions
[0])
713 instructions
[0] = desc
;
717 opcode_cache
[idx
] = desc
;
718 opcode_cache
[idx
].match
= insn
.bits();
721 return xlen
== 64 ? desc
.rv64
: desc
.rv32
;
724 void processor_t::register_insn(insn_desc_t desc
)
726 instructions
.push_back(desc
);
729 void processor_t::build_opcode_map()
732 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
733 if (lhs
.match
== rhs
.match
)
734 return lhs
.mask
> rhs
.mask
;
735 return lhs
.match
> rhs
.match
;
738 std::sort(instructions
.begin(), instructions
.end(), cmp());
740 for (size_t i
= 0; i
< OPCODE_CACHE_SIZE
; i
++)
741 opcode_cache
[i
] = {0, 0, &illegal_instruction
, &illegal_instruction
};
744 void processor_t::register_extension(extension_t
* x
)
746 for (auto insn
: x
->get_instructions())
749 for (auto disasm_insn
: x
->get_disasms())
750 disassembler
->add_insn(disasm_insn
);
752 throw std::logic_error("only one extension may be registered");
754 x
->set_processor(this);
757 void processor_t::register_base_instructions()
759 #define DECLARE_INSN(name, match, mask) \
760 insn_bits_t name##_match = (match), name##_mask = (mask);
761 #include "encoding.h"
764 #define DEFINE_INSN(name) \
765 REGISTER_INSN(this, name, name##_match, name##_mask)
766 #include "insn_list.h"
769 register_insn({0, 0, &illegal_instruction
, &illegal_instruction
});
773 bool processor_t::load(reg_t addr
, size_t len
, uint8_t* bytes
)
779 memset(bytes
, 0, len
);
780 bytes
[0] = get_field(state
.mip
, MIP_MSIP
);
789 bool processor_t::store(reg_t addr
, size_t len
, const uint8_t* bytes
)
795 state
.mip
= set_field(state
.mip
, MIP_MSIP
, bytes
[0]);
804 void processor_t::trigger_updated()
807 mmu
->check_triggers_fetch
= false;
808 mmu
->check_triggers_load
= false;
809 mmu
->check_triggers_store
= false;
811 for (unsigned i
= 0; i
< state
.num_triggers
; i
++) {
812 if (state
.mcontrol
[i
].execute
) {
813 mmu
->check_triggers_fetch
= true;
815 if (state
.mcontrol
[i
].load
) {
816 mmu
->check_triggers_load
= true;
818 if (state
.mcontrol
[i
].store
) {
819 mmu
->check_triggers_store
= true;