1 // See LICENSE for license details.
2 #ifndef _RISCV_DEBUG_MODULE_H
3 #define _RISCV_DEBUG_MODULE_H
17 HARTSTATUS_UNAVAILABLE
,
43 CMDERR_HALTRESUME
= 4,
50 class debug_module_data_t
: public abstract_device_t
53 debug_module_data_t();
55 bool load(reg_t addr
, size_t len
, uint8_t* bytes
);
56 bool store(reg_t addr
, size_t len
, const uint8_t* bytes
);
58 uint32_t read32(reg_t addr
) const;
59 void write32(reg_t addr
, uint32_t value
);
61 uint8_t data
[DEBUG_EXCHANGE_SIZE
];
64 class debug_module_t
: public abstract_device_t
67 debug_module_t(sim_t
*sim
);
69 void add_device(bus_t
*bus
);
71 bool load(reg_t addr
, size_t len
, uint8_t* bytes
);
72 bool store(reg_t addr
, size_t len
, const uint8_t* bytes
);
74 // Debug Module Interface that the debugger (in our case through JTAG DTM)
75 // uses to access the DM.
76 // Return true for success, false for failure.
77 bool dmi_read(unsigned address
, uint32_t *value
);
78 bool dmi_write(unsigned address
, uint32_t value
);
81 static const unsigned progsize
= 8;
85 uint8_t debug_rom_entry
[DEBUG_ROM_ENTRY_SIZE
];
86 uint8_t debug_rom_code
[DEBUG_ROM_CODE_SIZE
];
87 uint8_t debug_rom_exception
[DEBUG_ROM_EXCEPTION_SIZE
];
88 uint8_t program_buffer
[progsize
* 4];
90 debug_module_data_t dmdata
;
91 // Instruction that will be placed at the current hart's ROM entry address
92 // after the current action has completed.
96 void write32(uint8_t *rom
, unsigned int index
, uint32_t value
);
97 uint32_t read32(uint8_t *rom
, unsigned int index
);
99 dmcontrol_t dmcontrol
;
100 abstractcs_t abstractcs
;
103 processor_t
*current_proc() const;
105 bool perform_abstract_command();