riscv/decode.h

   1 #ifndef _RISCV_DECODE_H
   2 #define _RISCV_DECODE_H
   3
   4 #define __STDC_LIMIT_MACROS
   5 #include <stdint.h>
   6
   7 #include "config.h"
   8
   9 typedef int int128_t __attribute__((mode(TI)));
  10 typedef unsigned int uint128_t __attribute__((mode(TI)));
  11
  12 typedef int64_t sreg_t;
  13 typedef uint64_t reg_t;
  14 typedef uint64_t freg_t;
  15
  16 const int OPCODE_BITS = 7;
  17
  18 const int XPRID_BITS = 5;
  19 const int NXPR = 1 << XPRID_BITS;
  20
  21 const int FPR_BITS = 64;
  22 const int FPRID_BITS = 5;
  23 const int NFPR = 1 << FPRID_BITS;
  24
  25 const int IMM_BITS = 12;
  26 const int IMMLO_BITS = 7;
  27 const int TARGET_BITS = 25;
  28 const int SHAMT_BITS = 6;
  29 const int FUNCT_BITS = 3;
  30 const int FUNCTR_BITS = 7;
  31 const int FFUNCT_BITS = 5;
  32 const int BIGIMM_BITS = 20;
  33 const int BRANCH_ALIGN_BITS = 1;
  34 const int JUMP_ALIGN_BITS = 1;
  35
  36 #define SR_ET    0x0000000000000001ULL
  37 #define SR_PS    0x0000000000000004ULL
  38 #define SR_S     0x0000000000000008ULL
  39 #define SR_EF    0x0000000000000010ULL
  40 #define SR_UX    0x0000000000000020ULL
  41 #define SR_SX    0x0000000000000040ULL
  42 #define SR_IM    0x000000000000FF00ULL
  43 #define SR_ZERO  ~(SR_ET | SR_PS | SR_S | SR_EF | SR_UX | SR_SX | SR_IM)
  44 #define SR_IM_SHIFT 8
  45 #define TIMER_IRQ 7
  46
  47 #define FP_RD_NE  0
  48 #define FP_RD_0   1
  49 #define FP_RD_DN  2
  50 #define FP_RD_UP  3
  51 #define FSR_RD_SHIFT 5
  52 #define FSR_RD   (0x3 << FSR_RD_SHIFT)
  53
  54 #define FPEXC_NX 0x01
  55 #define FPEXC_UF 0x02
  56 #define FPEXC_OF 0x04
  57 #define FPEXC_DZ 0x02
  58 #define FPEXC_NV 0x10
  59
  60 #define FSR_AEXC_SHIFT 0
  61 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  62 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  63 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  64 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  65 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  66 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  67
  68 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
  69
  70 // note: bit fields are in little-endian order
  71 struct itype_t
  72 {
  73   unsigned opcode : OPCODE_BITS;
  74   unsigned funct : FUNCT_BITS;
  75   signed imm12 : IMM_BITS;
  76   unsigned rs1 : XPRID_BITS;
  77   unsigned rd : XPRID_BITS;
  78 };
  79
  80 struct btype_t
  81 {
  82   unsigned opcode : OPCODE_BITS;
  83   unsigned funct : FUNCT_BITS;
  84   unsigned immlo : IMMLO_BITS;
  85   unsigned rs2 : XPRID_BITS;
  86   unsigned rs1 : XPRID_BITS;
  87   signed immhi : IMM_BITS-IMMLO_BITS;
  88 };
  89
  90 struct jtype_t
  91 {
  92   unsigned jump_opcode : OPCODE_BITS;
  93   signed target : TARGET_BITS;
  94 };
  95
  96 struct rtype_t
  97 {
  98   unsigned opcode : OPCODE_BITS;
  99   unsigned funct : FUNCT_BITS;
 100   unsigned functr : FUNCTR_BITS;
 101   unsigned rs2 : XPRID_BITS;
 102   unsigned rs1 : XPRID_BITS;
 103   unsigned rd : XPRID_BITS;
 104 };
 105
 106 struct ltype_t
 107 {
 108   unsigned opcode : OPCODE_BITS;
 109   unsigned bigimm : BIGIMM_BITS;
 110   unsigned rd : XPRID_BITS;
 111 };
 112
 113 struct ftype_t
 114 {
 115   unsigned opcode : OPCODE_BITS;
 116   unsigned ffunct : FFUNCT_BITS;
 117   unsigned rs3 : FPRID_BITS;
 118   unsigned rs2 : FPRID_BITS;
 119   unsigned rs1 : FPRID_BITS;
 120   unsigned rd  : FPRID_BITS;
 121 };
 122
 123 union insn_t
 124 {
 125   itype_t itype;
 126   jtype_t jtype;
 127   rtype_t rtype;
 128   btype_t btype;
 129   ltype_t ltype;
 130   ftype_t ftype;
 131   uint32_t bits;
 132 };
 133
 134 #if 0
 135 #include <stdio.h>
 136 class trace_writeback
 137 {
 138 public:
 139   trace_writeback(reg_t* _rf, int _rd) : rf(_rf), rd(_rd) {}
 140
 141   reg_t operator = (reg_t rhs)
 142   {
 143     printf("R[%x] <= %llx\n",rd,(long long)rhs);
 144     rf[rd] = rhs;
 145     return rhs;
 146   }
 147
 148 private:
 149   reg_t* rf;
 150   int rd;
 151 };
 152
 153 #define do_writeback(rf,rd) trace_writeback(rf,rd)
 154 #else
 155 #define do_writeback(rf,rd) rf[rd]
 156 #endif
 157
 158 // helpful macros, etc
 159 #define RS1 XPR[insn.rtype.rs1]
 160 #define RS2 XPR[insn.rtype.rs2]
 161 #define RD do_writeback(XPR,insn.rtype.rd)
 162 #define RA do_writeback(XPR,1)
 163 #define FRS1 FPR[insn.ftype.rs1]
 164 #define FRS2 FPR[insn.ftype.rs2]
 165 #define FRS3 FPR[insn.ftype.rs3]
 166 #define FRD FPR[insn.ftype.rd]
 167 #define BIGIMM insn.ltype.bigimm
 168 #define SIMM insn.itype.imm12
 169 #define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
 170 #define SHAMT ((insn.itype.imm12 >> (IMM_BITS-6)) & 0x3F)
 171 #define SHAMTW ((insn.itype.imm12 >> (IMM_BITS-6)) & 0x1F)
 172 #define TARGET insn.jtype.target
 173 #define BRANCH_TARGET (npc + (BIMM << BRANCH_ALIGN_BITS))
 174 #define JUMP_TARGET (npc + (TARGET << JUMP_ALIGN_BITS))
 175 #define RM ((insn.ftype.ffunct & 4) ? (insn.ftype.ffunct & 3) : \
 176             ((fsr & FSR_RD) >> FSR_RD_SHIFT))
 177
 178 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
 179 #define xpr64 (xprlen == 64)
 180 #define require_xpr64 if(!xpr64) throw trap_illegal_instruction
 181 #define require_fp if(!(sr & SR_EF)) throw trap_fp_disabled
 182 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
 183 #define set_fp_exceptions ({ set_fsr(fsr | \
 184                                (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
 185                              softfloat_exceptionFlags = 0; })
 186
 187 static inline sreg_t sext32(int32_t arg)
 188 {
 189   return arg;
 190 }
 191
 192 #define sext_xprlen(x) ((sreg_t(x) << (64-xprlen)) >> (64-xprlen))
 193
 194 #endif