Have Debug memory kind of working again.
[riscv-isa-sim.git] / riscv / devices.cc
1 #include "devices.h"
2
3 void bus_t::add_device(reg_t addr, abstract_device_t* dev)
4 {
5 devices[-addr] = dev;
6 }
7
8 bool bus_t::load(reg_t addr, size_t len, uint8_t* bytes)
9 {
10 fprintf(stderr, "bus load(0x%lx, %ld)\n", addr, len);
11 auto it = devices.lower_bound(-addr);
12 if (it == devices.end()) {
13 fprintf(stderr, " -> false\n");
14 return false;
15 }
16 return it->second->load(addr - -it->first, len, bytes);
17 }
18
19 bool bus_t::store(reg_t addr, size_t len, const uint8_t* bytes)
20 {
21 auto it = devices.lower_bound(-addr);
22 if (it == devices.end())
23 return false;
24 return it->second->store(addr - -it->first, len, bytes);
25 }