Generate instruction decoder dynamically
[riscv-isa-sim.git] / riscv / insn_template.cc
1 // See LICENSE for license details.
2
3 #include "processor.h"
4 #include "config.h"
5 #include "sim.h"
6 #include "softfloat.h"
7 #include "platform.h" // softfloat isNaNF32UI, etc.
8 #include "internals.h" // ditto
9 #include <assert.h>
10
11 reg_t processor_t::rv32_NAME(insn_t insn, reg_t pc)
12 {
13 int xprlen = 32;
14 reg_t npc = sext_xprlen(pc + insn_length(OPCODE));
15 #include "insns/NAME.h"
16 return npc;
17 }
18
19 reg_t processor_t::rv64_NAME(insn_t insn, reg_t pc)
20 {
21 int xprlen = 64;
22 reg_t npc = sext_xprlen(pc + insn_length(OPCODE));
23 #include "insns/NAME.h"
24 return npc;
25 }