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[xcc,sim,opcodes] more rvc instructions and bug fixes
[riscv-isa-sim.git]
/
riscv
/
insns
/
c_addi.h
1
require_rvc
;
2
CRD
=
sext_xprlen
(
CRS2
+
CIMM6
);
projects / riscv-isa-sim.git / blob