[xcc,sim,opcodes] added more RVC instructions
[riscv-isa-sim.git] / riscv / insns / c_addi.h
1 require_rvc;
2 if(CRD_REGNUM == 0)
3 {
4 reg_t temp = npc;
5 npc = CRS1;
6 if(CIMM6 & 0x20)
7 RA = temp;
8 }
9 else
10 CRD = sext_xprlen(CRS2 + CIMM6);