riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "htif.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
  23   : sim(sim), ext(NULL), disassembler(new disassembler_t),
  24     id(id), run(false), debug(false)
  25 {
  26   parse_isa_string(isa);
  27
  28   mmu = new mmu_t(sim->mem, sim->memsz);
  29   mmu->set_processor(this);
  30
  31   reset(true);
  32
  33   register_base_instructions();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* isa)
  58 {
  59   const char* p = isa;
  60   const char* all_subsets = "IMAFDC";
  61   std::string tmp;
  62
  63   max_xlen = 64;
  64   cpuid = reg_t(2) << 62;
  65
  66   if (strncmp(p, "RV32", 4) == 0)
  67     max_xlen = 32, cpuid = 0, p += 4;
  68   else if (strncmp(p, "RV64", 4) == 0)
  69     p += 4;
  70   else if (strncmp(p, "RV", 2) == 0)
  71     p += 2;
  72
  73   if (!*p) {
  74     p = all_subsets;
  75   } else if (*p == 'G') { // treat "G" as "IMAFD"
  76     tmp = std::string("IMAFD") + (p+1);
  77     p = &tmp[0];
  78   } else if (*p != 'I') {
  79     bad_isa_string(isa);
  80   }
  81
  82   cpuid |= 1L << ('S' - 'A'); // advertise support for supervisor mode
  83
  84   while (*p) {
  85     cpuid |= 1L << (*p - 'A');
  86
  87     if (auto next = strchr(all_subsets, *p)) {
  88       all_subsets = next + 1;
  89       p++;
  90     } else if (*p == 'X') {
  91       const char* ext = p+1, *end = ext;
  92       while (islower(*end))
  93         end++;
  94       register_extension(find_extension(std::string(ext, end - ext).c_str())());
  95       p = end;
  96     } else {
  97       bad_isa_string(isa);
  98     }
  99   }
 100
 101   if (supports_extension('D') && !supports_extension('F'))
 102     bad_isa_string(isa);
 103 }
 104
 105 void state_t::reset()
 106 {
 107   memset(this, 0, sizeof(*this));
 108   mstatus = set_field(mstatus, MSTATUS_PRV, PRV_M);
 109   mstatus = set_field(mstatus, MSTATUS_PRV1, PRV_U);
 110   mstatus = set_field(mstatus, MSTATUS_PRV2, PRV_U);
 111   pc = DEFAULT_MTVEC + 0x100;
 112   load_reservation = -1;
 113 }
 114
 115 void processor_t::set_debug(bool value)
 116 {
 117   debug = value;
 118   if (ext)
 119     ext->set_debug(value);
 120 }
 121
 122 void processor_t::set_histogram(bool value)
 123 {
 124   histogram_enabled = value;
 125 #ifndef RISCV_ENABLE_HISTOGRAM
 126   if (value) {
 127     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 128     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 129   }
 130 #endif
 131 }
 132
 133 void processor_t::reset(bool value)
 134 {
 135   if (run == !value)
 136     return;
 137   run = !value;
 138
 139   state.reset();
 140   set_csr(CSR_MSTATUS, state.mstatus);
 141
 142   if (ext)
 143     ext->reset(); // reset the extension
 144 }
 145
 146 void processor_t::raise_interrupt(reg_t which)
 147 {
 148   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 149 }
 150
 151 void processor_t::take_interrupt()
 152 {
 153   int priv = get_field(state.mstatus, MSTATUS_PRV);
 154   int ie = get_field(state.mstatus, MSTATUS_IE);
 155   reg_t interrupts = state.mie & state.mip;
 156
 157   if (priv < PRV_M || (priv == PRV_M && ie)) {
 158     if (interrupts & MIP_MSIP)
 159       raise_interrupt(IRQ_SOFT);
 160
 161     if (interrupts & MIP_MTIP)
 162       raise_interrupt(IRQ_TIMER);
 163
 164     if (state.fromhost != 0)
 165       raise_interrupt(IRQ_HOST);
 166   }
 167
 168   if (priv < PRV_S || (priv == PRV_S && ie)) {
 169     if (interrupts & MIP_SSIP)
 170       raise_interrupt(IRQ_SOFT);
 171
 172     if (interrupts & MIP_STIP)
 173       raise_interrupt(IRQ_TIMER);
 174   }
 175 }
 176
 177 void processor_t::check_timer()
 178 {
 179   if (sim->rtc >= state.mtimecmp)
 180     state.mip |= MIP_MTIP;
 181 }
 182
 183 void processor_t::push_privilege_stack()
 184 {
 185   reg_t s = state.mstatus;
 186   s = set_field(s, MSTATUS_PRV2, get_field(state.mstatus, MSTATUS_PRV1));
 187   s = set_field(s, MSTATUS_IE2, get_field(state.mstatus, MSTATUS_IE1));
 188   s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV));
 189   s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE));
 190   s = set_field(s, MSTATUS_PRV, PRV_M);
 191   s = set_field(s, MSTATUS_MPRV, 0);
 192   s = set_field(s, MSTATUS_IE, 0);
 193   set_csr(CSR_MSTATUS, s);
 194 }
 195
 196 void processor_t::pop_privilege_stack()
 197 {
 198   reg_t s = state.mstatus;
 199   s = set_field(s, MSTATUS_PRV, get_field(state.mstatus, MSTATUS_PRV1));
 200   s = set_field(s, MSTATUS_IE, get_field(state.mstatus, MSTATUS_IE1));
 201   s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV2));
 202   s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE2));
 203   s = set_field(s, MSTATUS_PRV2, PRV_U);
 204   s = set_field(s, MSTATUS_IE2, 1);
 205   set_csr(CSR_MSTATUS, s);
 206 }
 207
 208 void processor_t::take_trap(trap_t& t, reg_t epc)
 209 {
 210   if (debug)
 211     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 212             id, t.name(), epc);
 213
 214   state.pc = DEFAULT_MTVEC + 0x40 * get_field(state.mstatus, MSTATUS_PRV);
 215   push_privilege_stack();
 216   yield_load_reservation();
 217   state.mcause = t.cause();
 218   state.mepc = epc;
 219   t.side_effects(&state); // might set badvaddr etc.
 220 }
 221
 222 void processor_t::deliver_ipi()
 223 {
 224   state.mip |= MIP_MSIP;
 225 }
 226
 227 void processor_t::disasm(insn_t insn)
 228 {
 229   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 230   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 231           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 232 }
 233
 234 static bool validate_priv(reg_t priv)
 235 {
 236   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 237 }
 238
 239 static bool validate_vm(int max_xlen, reg_t vm)
 240 {
 241   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 242     return true;
 243   if (max_xlen == 32 && vm == VM_SV32)
 244     return true;
 245   return vm == VM_MBARE;
 246 }
 247
 248 void processor_t::set_csr(int which, reg_t val)
 249 {
 250   switch (which)
 251   {
 252     case CSR_FFLAGS:
 253       dirty_fp_state;
 254       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 255       break;
 256     case CSR_FRM:
 257       dirty_fp_state;
 258       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 259       break;
 260     case CSR_FCSR:
 261       dirty_fp_state;
 262       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 263       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 264       break;
 265     case CSR_MTIME:
 266     case CSR_STIMEW:
 267       // this implementation ignores writes to MTIME
 268       break;
 269     case CSR_MTIMEH:
 270     case CSR_STIMEHW:
 271       // this implementation ignores writes to MTIME
 272       break;
 273     case CSR_TIMEW:
 274       val -= sim->rtc;
 275       if (xlen == 32)
 276         state.sutime_delta = (uint32_t)val | (state.sutime_delta >> 32 << 32);
 277       else
 278         state.sutime_delta = val;
 279       break;
 280     case CSR_TIMEHW:
 281       val = ((val << 32) - sim->rtc) >> 32;
 282       state.sutime_delta = (val << 32) | (uint32_t)state.sutime_delta;
 283       break;
 284     case CSR_CYCLEW:
 285     case CSR_INSTRETW:
 286       val -= state.minstret;
 287       if (xlen == 32)
 288         state.suinstret_delta = (uint32_t)val | (state.suinstret_delta >> 32 << 32);
 289       else
 290         state.suinstret_delta = val;
 291       break;
 292     case CSR_CYCLEHW:
 293     case CSR_INSTRETHW:
 294       val = ((val << 32) - state.minstret) >> 32;
 295       state.suinstret_delta = (val << 32) | (uint32_t)state.suinstret_delta;
 296       break;
 297     case CSR_MSTATUS: {
 298       if ((val ^ state.mstatus) & (MSTATUS_VM | MSTATUS_PRV | MSTATUS_PRV1 | MSTATUS_MPRV))
 299         mmu->flush_tlb();
 300
 301       reg_t mask = MSTATUS_IE | MSTATUS_IE1 | MSTATUS_IE2 | MSTATUS_MPRV
 302                    | MSTATUS_FS | (ext ? MSTATUS_XS : 0);
 303
 304       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 305         mask |= MSTATUS_VM;
 306       if (validate_priv(get_field(val, MSTATUS_PRV)))
 307         mask |= MSTATUS_PRV;
 308       if (validate_priv(get_field(val, MSTATUS_PRV1)))
 309         mask |= MSTATUS_PRV1;
 310       if (validate_priv(get_field(val, MSTATUS_PRV2)))
 311         mask |= MSTATUS_PRV2;
 312
 313       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 314
 315       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 316       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 317       if (max_xlen == 32)
 318         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 319       else
 320         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 321
 322       // spike supports the notion of xlen < max_xlen, but current priv spec
 323       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 324       xlen = max_xlen;
 325       break;
 326     }
 327     case CSR_MIP: {
 328       reg_t mask = MIP_SSIP | MIP_MSIP | MIP_STIP;
 329       state.mip = (state.mip & ~mask) | (val & mask);
 330       break;
 331     }
 332     case CSR_MIE: {
 333       reg_t mask = MIP_SSIP | MIP_MSIP | MIP_STIP | MIP_MTIP;
 334       state.mie = (state.mie & ~mask) | (val & mask);
 335       break;
 336     }
 337     case CSR_SSTATUS: {
 338       reg_t ms = state.mstatus;
 339       ms = set_field(ms, MSTATUS_IE, get_field(val, SSTATUS_IE));
 340       ms = set_field(ms, MSTATUS_IE1, get_field(val, SSTATUS_PIE));
 341       ms = set_field(ms, MSTATUS_PRV1, get_field(val, SSTATUS_PS));
 342       ms = set_field(ms, MSTATUS_FS, get_field(val, SSTATUS_FS));
 343       ms = set_field(ms, MSTATUS_XS, get_field(val, SSTATUS_XS));
 344       ms = set_field(ms, MSTATUS_MPRV, get_field(val, SSTATUS_MPRV));
 345       return set_csr(CSR_MSTATUS, ms);
 346     }
 347     case CSR_SIP: {
 348       reg_t mask = MIP_SSIP;
 349       state.mip = (state.mip & ~mask) | (val & mask);
 350       break;
 351     }
 352     case CSR_SIE: {
 353       reg_t mask = MIP_SSIP | MIP_STIP;
 354       state.mie = (state.mie & ~mask) | (val & mask);
 355       break;
 356     }
 357     case CSR_SEPC: state.sepc = val; break;
 358     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 359     case CSR_SPTBR: state.sptbr = zext_xlen(val & -PGSIZE); break;
 360     case CSR_SSCRATCH: state.sscratch = val; break;
 361     case CSR_MEPC: state.mepc = val; break;
 362     case CSR_MSCRATCH: state.mscratch = val; break;
 363     case CSR_MCAUSE: state.mcause = val; break;
 364     case CSR_MBADADDR: state.mbadaddr = val; break;
 365     case CSR_MTIMECMP:
 366       state.mip &= ~MIP_MTIP;
 367       state.mtimecmp = val;
 368       break;
 369     case CSR_SEND_IPI: sim->send_ipi(val); break;
 370     case CSR_MTOHOST:
 371       if (state.tohost == 0)
 372         state.tohost = val;
 373       break;
 374     case CSR_MFROMHOST: state.fromhost = val; break;
 375   }
 376 }
 377
 378 reg_t processor_t::get_csr(int which)
 379 {
 380   switch (which)
 381   {
 382     case CSR_FFLAGS:
 383       require_fp;
 384       if (!supports_extension('F'))
 385         break;
 386       return state.fflags;
 387     case CSR_FRM:
 388       require_fp;
 389       if (!supports_extension('F'))
 390         break;
 391       return state.frm;
 392     case CSR_FCSR:
 393       require_fp;
 394       if (!supports_extension('F'))
 395         break;
 396       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 397     case CSR_MTIME:
 398     case CSR_STIME:
 399     case CSR_STIMEW:
 400       return sim->rtc;
 401     case CSR_MTIMEH:
 402     case CSR_STIMEH:
 403     case CSR_STIMEHW:
 404       return sim->rtc >> 32;
 405     case CSR_TIME:
 406     case CSR_TIMEW:
 407       return sim->rtc + state.sutime_delta;
 408     case CSR_CYCLE:
 409     case CSR_CYCLEW:
 410     case CSR_INSTRET:
 411     case CSR_INSTRETW:
 412       return state.minstret + state.suinstret_delta;
 413     case CSR_TIMEH:
 414     case CSR_TIMEHW:
 415       if (xlen == 64)
 416         break;
 417       return (sim->rtc + state.sutime_delta) >> 32;
 418     case CSR_CYCLEH:
 419     case CSR_INSTRETH:
 420     case CSR_CYCLEHW:
 421     case CSR_INSTRETHW:
 422       if (xlen == 64)
 423         break;
 424       return (state.minstret + state.suinstret_delta) >> 32;
 425     case CSR_SSTATUS: {
 426       reg_t ss = 0;
 427       ss = set_field(ss, SSTATUS_IE, get_field(state.mstatus, MSTATUS_IE));
 428       ss = set_field(ss, SSTATUS_PIE, get_field(state.mstatus, MSTATUS_IE1));
 429       ss = set_field(ss, SSTATUS_PS, get_field(state.mstatus, MSTATUS_PRV1));
 430       ss = set_field(ss, SSTATUS_FS, get_field(state.mstatus, MSTATUS_FS));
 431       ss = set_field(ss, SSTATUS_XS, get_field(state.mstatus, MSTATUS_XS));
 432       ss = set_field(ss, SSTATUS_MPRV, get_field(state.mstatus, MSTATUS_MPRV));
 433       if (get_field(state.mstatus, MSTATUS64_SD))
 434         ss = set_field(ss, (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD), 1);
 435       return ss;
 436     }
 437     case CSR_SIP: return state.mip & (MIP_SSIP | MIP_STIP);
 438     case CSR_SIE: return state.mie & (MIP_SSIP | MIP_STIP);
 439     case CSR_SEPC: return state.sepc;
 440     case CSR_SBADADDR: return state.sbadaddr;
 441     case CSR_STVEC: return state.stvec;
 442     case CSR_SCAUSE:
 443       if (max_xlen > xlen)
 444         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 445       return state.scause;
 446     case CSR_SPTBR: return state.sptbr;
 447     case CSR_SASID: return 0;
 448     case CSR_SSCRATCH: return state.sscratch;
 449     case CSR_MSTATUS: return state.mstatus;
 450     case CSR_MIP: return state.mip;
 451     case CSR_MIE: return state.mie;
 452     case CSR_MEPC: return state.mepc;
 453     case CSR_MSCRATCH: return state.mscratch;
 454     case CSR_MCAUSE: return state.mcause;
 455     case CSR_MBADADDR: return state.mbadaddr;
 456     case CSR_MTIMECMP: return state.mtimecmp;
 457     case CSR_MCPUID: return cpuid;
 458     case CSR_MIMPID: return IMPL_ROCKET;
 459     case CSR_MHARTID: return id;
 460     case CSR_MTVEC: return DEFAULT_MTVEC;
 461     case CSR_MTDELEG: return 0;
 462     case CSR_MTOHOST:
 463       sim->get_htif()->tick(); // not necessary, but faster
 464       return state.tohost;
 465     case CSR_MFROMHOST:
 466       sim->get_htif()->tick(); // not necessary, but faster
 467       return state.fromhost;
 468     case CSR_SEND_IPI: return 0;
 469     case CSR_UARCH0:
 470     case CSR_UARCH1:
 471     case CSR_UARCH2:
 472     case CSR_UARCH3:
 473     case CSR_UARCH4:
 474     case CSR_UARCH5:
 475     case CSR_UARCH6:
 476     case CSR_UARCH7:
 477     case CSR_UARCH8:
 478     case CSR_UARCH9:
 479     case CSR_UARCH10:
 480     case CSR_UARCH11:
 481     case CSR_UARCH12:
 482     case CSR_UARCH13:
 483     case CSR_UARCH14:
 484     case CSR_UARCH15:
 485       return 0;
 486   }
 487   throw trap_illegal_instruction();
 488 }
 489
 490 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 491 {
 492   throw trap_illegal_instruction();
 493 }
 494
 495 insn_func_t processor_t::decode_insn(insn_t insn)
 496 {
 497   // look up opcode in hash table
 498   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 499   insn_desc_t desc = opcode_cache[idx];
 500
 501   if (unlikely(insn.bits() != desc.match)) {
 502     // fall back to linear search
 503     insn_desc_t* p = &instructions[0];
 504     while ((insn.bits() & p->mask) != p->match)
 505       p++;
 506     desc = *p;
 507
 508     if (p->mask != 0 && p > &instructions[0]) {
 509       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 510         // move to front of opcode list to reduce miss penalty
 511         while (--p >= &instructions[0])
 512           *(p+1) = *p;
 513         instructions[0] = desc;
 514       }
 515     }
 516
 517     opcode_cache[idx] = desc;
 518     opcode_cache[idx].match = insn.bits();
 519   }
 520
 521   return xlen == 64 ? desc.rv64 : desc.rv32;
 522 }
 523
 524 void processor_t::register_insn(insn_desc_t desc)
 525 {
 526   instructions.push_back(desc);
 527 }
 528
 529 void processor_t::build_opcode_map()
 530 {
 531   struct cmp {
 532     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 533       if (lhs.match == rhs.match)
 534         return lhs.mask > rhs.mask;
 535       return lhs.match > rhs.match;
 536     }
 537   };
 538   std::sort(instructions.begin(), instructions.end(), cmp());
 539
 540   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 541     opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
 542 }
 543
 544 void processor_t::register_extension(extension_t* x)
 545 {
 546   for (auto insn : x->get_instructions())
 547     register_insn(insn);
 548   build_opcode_map();
 549   for (auto disasm_insn : x->get_disasms())
 550     disassembler->add_insn(disasm_insn);
 551   if (ext != NULL)
 552     throw std::logic_error("only one extension may be registered");
 553   ext = x;
 554   x->set_processor(this);
 555 }
 556
 557 void processor_t::register_base_instructions()
 558 {
 559   #define DECLARE_INSN(name, match, mask) \
 560     insn_bits_t name##_match = (match), name##_mask = (mask);
 561   #include "encoding.h"
 562   #undef DECLARE_INSN
 563
 564   #define DEFINE_INSN(name) \
 565     REGISTER_INSN(this, name, name##_match, name##_mask)
 566   #include "insn_list.h"
 567   #undef DEFINE_INSN
 568
 569   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 570   build_opcode_map();
 571 }