riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "common.h"
   5 #include "config.h"
   6 #include "sim.h"
   7 #include "disasm.h"
   8 #include <inttypes.h>
   9 #include <cmath>
  10 #include <cstdlib>
  11 #include <iostream>
  12 #include <assert.h>
  13
  14 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
  15   : sim(*_sim), mmu(*_mmu), id(_id), utidx(0)
  16 {
  17   reset(true);
  18
  19   // create microthreads
  20   for (int i=0; i<MAX_UTS; i++)
  21     uts[i] = new processor_t(&sim, &mmu, id, i);
  22 }
  23
  24 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id,
  25                          uint32_t _utidx)
  26   : sim(*_sim), mmu(*_mmu), id(_id)
  27 {
  28   reset(true);
  29   set_pcr(PCR_SR, SR_U64 | SR_EF | SR_EV);
  30   utidx = _utidx;
  31
  32   // microthreads don't possess their own microthreads
  33   for (int i=0; i<MAX_UTS; i++)
  34     uts[i] = NULL;
  35 }
  36
  37 processor_t::~processor_t()
  38 {
  39 }
  40
  41 void processor_t::reset(bool value)
  42 {
  43   if (run == !value)
  44     return;
  45   run = !value;
  46
  47   // the ISA guarantees on boot that the PC is 0x2000 and the the processor
  48   // is in supervisor mode, and in 64-bit mode, if supported, with traps
  49   // and virtual memory disabled.
  50   sr = 0;
  51   set_pcr(PCR_SR, SR_S | SR_S64 | SR_IM);
  52   pc = 0x2000;
  53
  54   // the following state is undefined upon boot-up,
  55   // but we zero it for determinism
  56   XPR.reset();
  57   FPR.reset();
  58
  59   evec = 0;
  60   epc = 0;
  61   badvaddr = 0;
  62   cause = 0;
  63   pcr_k0 = 0;
  64   pcr_k1 = 0;
  65   count = 0;
  66   compare = 0;
  67   cycle = 0;
  68   set_fsr(0);
  69
  70   // vector stuff
  71   vecbanks = 0xff;
  72   vecbanks_count = 8;
  73   utidx = -1;
  74   vlmax = 32;
  75   vl = 0;
  76   nxfpr_bank = 256;
  77   nxpr_use = 32;
  78   nfpr_use = 32;
  79 }
  80
  81 void processor_t::set_fsr(uint32_t val)
  82 {
  83   fsr = val & ~FSR_ZERO; // clear FSR bits that read as zero
  84 }
  85
  86 void processor_t::vcfg()
  87 {
  88   if (nxpr_use + nfpr_use < 2)
  89     vlmax = nxfpr_bank * vecbanks_count;
  90   else
  91     vlmax = (nxfpr_bank / (nxpr_use + nfpr_use - 1)) * vecbanks_count;
  92
  93   vlmax = std::min(vlmax, MAX_UTS);
  94 }
  95
  96 void processor_t::setvl(int vlapp)
  97 {
  98   vl = std::min(vlmax, vlapp);
  99 }
 100
 101 void processor_t::take_interrupt()
 102 {
 103   uint32_t interrupts = (sr & SR_IP) >> SR_IP_SHIFT;
 104   interrupts &= (sr & SR_IM) >> SR_IM_SHIFT;
 105
 106   if(interrupts && (sr & SR_ET))
 107     for(int i = 0; ; i++, interrupts >>= 1)
 108       if(interrupts & 1)
 109         throw interrupt_t(i);
 110 }
 111
 112 void processor_t::step(size_t n, bool noisy)
 113 {
 114   if(!run)
 115     return;
 116
 117   size_t i = 0;
 118   try
 119   {
 120     take_interrupt();
 121
 122     mmu_t& _mmu = mmu;
 123     reg_t npc = pc;
 124
 125     // execute_insn fetches and executes one instruction
 126     #define execute_insn(noisy) \
 127       do { \
 128         mmu_t::insn_fetch_t fetch = _mmu.load_insn(npc, sr & SR_EC); \
 129         if(noisy) disasm(fetch.insn, npc); \
 130         npc = fetch.func(this, fetch.insn, npc); \
 131         pc = npc; \
 132       } while(0)
 133
 134     if(noisy) for( ; i < n; i++) // print out instructions as we go
 135       execute_insn(true);
 136     else
 137     {
 138       // unrolled for speed
 139       for( ; n > 3 && i < n-3; i+=4)
 140       {
 141         execute_insn(false);
 142         execute_insn(false);
 143         execute_insn(false);
 144         execute_insn(false);
 145       }
 146       for( ; i < n; i++)
 147         execute_insn(false);
 148     }
 149   }
 150   catch(trap_t t)
 151   {
 152     // an exception occurred in the target processor
 153     take_trap(t,noisy);
 154   }
 155   catch(interrupt_t t)
 156   {
 157     take_trap((1ULL << (8*sizeof(reg_t)-1)) + t.i, noisy);
 158   }
 159   catch(vt_command_t cmd)
 160   {
 161     // this microthread has finished
 162     assert(cmd == vt_command_stop);
 163   }
 164
 165   cycle += i;
 166
 167   // update timer and possibly register a timer interrupt
 168   uint32_t old_count = count;
 169   count += i;
 170   if(old_count < compare && uint64_t(old_count) + i >= compare)
 171     set_interrupt(IRQ_TIMER, true);
 172 }
 173
 174 void processor_t::take_trap(reg_t t, bool noisy)
 175 {
 176   if(noisy)
 177   {
 178     if ((sreg_t)t < 0)
 179       printf("core %3d: interrupt %lld, pc 0x%016llx\n",
 180              id, (long long)(t << 1 >> 1), (unsigned long long)pc);
 181     else
 182       printf("core %3d: trap %s, pc 0x%016llx\n",
 183              id, trap_name(trap_t(t)), (unsigned long long)pc);
 184   }
 185
 186   // switch to supervisor, set previous supervisor bit, disable traps
 187   set_pcr(PCR_SR, (((sr & ~SR_ET) | SR_S) & ~SR_PS) | ((sr & SR_S) ? SR_PS : 0));
 188   cause = t;
 189   epc = pc;
 190   pc = evec;
 191   badvaddr = mmu.get_badvaddr();
 192 }
 193
 194 void processor_t::deliver_ipi()
 195 {
 196   if (run)
 197     set_pcr(PCR_CLR_IPI, 1);
 198 }
 199
 200 void processor_t::disasm(insn_t insn, reg_t pc)
 201 {
 202   // the disassembler is stateless, so we share it
 203   static disassembler disasm;
 204   printf("core %3d: 0x%016llx (0x%08x) %s\n", id, (unsigned long long)pc,
 205          insn.bits, disasm.disassemble(insn).c_str());
 206 }
 207
 208 void processor_t::set_pcr(int which, reg_t val)
 209 {
 210   switch (which)
 211   {
 212     case PCR_SR:
 213       sr = (val & ~SR_IP) | (sr & SR_IP);
 214 #ifndef RISCV_ENABLE_64BIT
 215       sr &= ~(SR_S64 | SR_U64);
 216 #endif
 217 #ifndef RISCV_ENABLE_FPU
 218       sr &= ~SR_EF;
 219 #endif
 220 #ifndef RISCV_ENABLE_RVC
 221       sr &= ~SR_EC;
 222 #endif
 223 #ifndef RISCV_ENABLE_VEC
 224       sr &= ~SR_EV;
 225 #endif
 226       sr &= ~SR_ZERO;
 227       mmu.set_sr(sr);
 228       break;
 229     case PCR_EPC:
 230       epc = val;
 231       break;
 232     case PCR_EVEC:
 233       evec = val;
 234       break;
 235     case PCR_COUNT:
 236       count = val;
 237       break;
 238     case PCR_COMPARE:
 239       set_interrupt(IRQ_TIMER, false);
 240       compare = val;
 241       break;
 242     case PCR_PTBR:
 243       mmu.set_ptbr(val);
 244       break;
 245     case PCR_SEND_IPI:
 246       sim.send_ipi(val);
 247       break;
 248     case PCR_CLR_IPI:
 249       set_interrupt(IRQ_IPI, val & 1);
 250       break;
 251     case PCR_K0:
 252       pcr_k0 = val;
 253       break;
 254     case PCR_K1:
 255       pcr_k1 = val;
 256       break;
 257     case PCR_VECBANK:
 258       vecbanks = val & 0xff;
 259       vecbanks_count = __builtin_popcountll(vecbanks);
 260       break;
 261     case PCR_TOHOST:
 262       if (tohost == 0)
 263         tohost = val;
 264       break;
 265     case PCR_FROMHOST:
 266       set_interrupt(IRQ_HOST, val != 0);
 267       fromhost = val;
 268       break;
 269   }
 270 }
 271
 272 reg_t processor_t::get_pcr(int which)
 273 {
 274   switch (which)
 275   {
 276     case PCR_SR:
 277       return sr;
 278     case PCR_EPC:
 279       return epc;
 280     case PCR_BADVADDR:
 281       return badvaddr;
 282     case PCR_EVEC:
 283       return evec;
 284     case PCR_COUNT:
 285       return count;
 286     case PCR_COMPARE:
 287       return compare;
 288     case PCR_CAUSE:
 289       return cause;
 290     case PCR_PTBR:
 291       return mmu.get_ptbr();
 292     case PCR_COREID:
 293       return id;
 294     case PCR_IMPL:
 295       return 1;
 296     case PCR_K0:
 297       return pcr_k0;
 298     case PCR_K1:
 299       return pcr_k1;
 300     case PCR_VECBANK:
 301       return vecbanks;
 302     case PCR_TOHOST:
 303       return tohost;
 304     case PCR_FROMHOST:
 305       return fromhost;
 306   }
 307   return -1;
 308 }
 309
 310 void processor_t::set_interrupt(int which, bool on)
 311 {
 312   uint32_t mask = (1 << (which + SR_IP_SHIFT)) & SR_IP;
 313   if (on)
 314     sr |= mask;
 315   else
 316     sr &= ~mask;
 317 }