1 // See LICENSE for license details.
19 #include "sv_insn_redirect.h"
25 processor_t::processor_t(const char* isa
, simif_t
* sim
, uint32_t id
,
27 : debug(false), halt_request(false), sim(sim
), ext(NULL
), id(id
),
28 halt_on_reset(halt_on_reset
), last_pc(1), executions(1)
33 parse_isa_string(isa
);
34 register_base_instructions();
37 mmu
= new sv_mmu_t(sim
, this);
39 mmu
= new mmu_t(sim
, this);
42 disassembler
= new disassembler_t(max_xlen
);
44 for (auto disasm_insn
: ext
->get_disasms())
45 disassembler
->add_insn(disasm_insn
);
50 processor_t::~processor_t()
52 #ifdef RISCV_ENABLE_HISTOGRAM
53 if (histogram_enabled
)
55 fprintf(stderr
, "PC Histogram size:%zu\n", pc_histogram
.size());
56 for (auto it
: pc_histogram
)
57 fprintf(stderr
, "%0" PRIx64
" %" PRIu64
"\n", it
.first
, it
.second
);
65 static void bad_isa_string(const char* isa
)
67 fprintf(stderr
, "error: bad --isa option %s\n", isa
);
71 void processor_t::parse_isa_string(const char* str
)
73 std::string lowercase
, tmp
;
74 for (const char *r
= str
; *r
; r
++)
75 lowercase
+= std::tolower(*r
);
77 const char* p
= lowercase
.c_str();
78 const char* all_subsets
= "imafdqc";
81 state
.misa
= reg_t(2) << 62;
83 if (strncmp(p
, "rv32", 4) == 0)
84 max_xlen
= 32, state
.misa
= reg_t(1) << 30, p
+= 4;
85 else if (strncmp(p
, "rv64", 4) == 0)
87 else if (strncmp(p
, "rv", 2) == 0)
92 } else if (*p
== 'g') { // treat "G" as "IMAFD"
93 tmp
= std::string("imafd") + (p
+1);
95 } else if (*p
!= 'i') {
99 isa_string
= "rv" + std::to_string(max_xlen
) + p
;
100 state
.misa
|= 1L << ('s' - 'a'); // advertise support for supervisor mode
101 state
.misa
|= 1L << ('u' - 'a'); // advertise support for user mode
104 state
.misa
|= 1L << (*p
- 'a');
106 if (auto next
= strchr(all_subsets
, *p
)) {
107 all_subsets
= next
+ 1;
109 } else if (*p
== 'x') {
110 const char* ext
= p
+1, *end
= ext
;
111 while (islower(*end
))
113 register_extension(find_extension(std::string(ext
, end
- ext
).c_str())());
120 if (supports_extension('D') && !supports_extension('F'))
123 if (supports_extension('Q') && !supports_extension('D'))
126 if (supports_extension('Q') && max_xlen
< 64)
129 max_isa
= state
.misa
;
132 void state_t::reset(reg_t max_isa
)
134 memset(this, 0, sizeof(*this));
139 for (unsigned int i
= 0; i
< num_triggers
; i
++)
140 mcontrol
[i
].type
= 2;
142 // set SV CSR banks to default (full) sizes
147 msv
.vl
= msv
.mvl
= 0;
148 ssv
.vl
= ssv
.mvl
= 0;
149 usv
.vl
= usv
.mvl
= 0;
150 // SUBVL all 1, including in xesvstate
154 mesvstate
= sesvstate
= 0;
158 void sv_shape_t::setup_map()
161 int lims
[3] = {xsz
, ysz
, zsz
};
162 int idxs
[3] = {0,0,0};
165 case SV_SHAPE_PERM_XYZ
: order
[0] = 0; order
[1] = 1; order
[2] = 2; break;
166 case SV_SHAPE_PERM_XZY
: order
[0] = 0; order
[1] = 2; order
[2] = 1; break;
167 case SV_SHAPE_PERM_YXZ
: order
[0] = 1; order
[1] = 0; order
[2] = 2; break;
168 case SV_SHAPE_PERM_YZX
: order
[0] = 1; order
[1] = 2; order
[2] = 0; break;
169 case SV_SHAPE_PERM_ZXY
: order
[0] = 2; order
[1] = 0; order
[2] = 1; break;
170 case SV_SHAPE_PERM_ZYX
: order
[0] = 2; order
[1] = 1; order
[2] = 0; break;
171 default: throw trap_illegal_instruction(0);
173 for (int i
= 0; i
< 128; i
++)
175 uint8_t new_idx
= idxs
[0] + idxs
[1] * xsz
+ idxs
[2] * xsz
* ysz
;
177 for (int j
= 0; j
< 3; j
++)
179 idxs
[order
[j
]] = idxs
[order
[j
]] + 1;
180 if (idxs
[order
[j
]] != lims
[order
[j
]]) {
188 int state_t::sv_csr_sz()
196 sv_csr_t
&state_t::sv()
205 sv_shape_t
* state_t::get_shape(reg_t reg
, bool pred
)
207 if (prv
== PRV_M
|| prv
== PRV_S
|| reg
== 0) {
210 for (int i
= 0; i
< 3; i
++) {
211 if (remap
[i
].regidx
== reg
&& remap
[i
].pred
== pred
) {
218 void processor_t::set_debug(bool value
)
222 ext
->set_debug(value
);
225 void processor_t::set_histogram(bool value
)
227 histogram_enabled
= value
;
228 #ifndef RISCV_ENABLE_HISTOGRAM
230 fprintf(stderr
, "PC Histogram support has not been properly enabled;");
231 fprintf(stderr
, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
236 void processor_t::reset()
238 state
.reset(max_isa
);
239 state
.dcsr
.halt
= halt_on_reset
;
240 halt_on_reset
= false;
241 set_csr(CSR_MSTATUS
, state
.mstatus
);
244 ext
->reset(); // reset the extension
250 // Count number of contiguous 0 bits starting from the LSB.
251 static int ctz(reg_t val
)
255 while ((val
& 1) == 0)
260 void processor_t::take_interrupt(reg_t pending_interrupts
)
262 reg_t mie
= get_field(state
.mstatus
, MSTATUS_MIE
);
263 reg_t m_enabled
= state
.prv
< PRV_M
|| (state
.prv
== PRV_M
&& mie
);
264 reg_t enabled_interrupts
= pending_interrupts
& ~state
.mideleg
& -m_enabled
;
266 reg_t sie
= get_field(state
.mstatus
, MSTATUS_SIE
);
267 reg_t s_enabled
= state
.prv
< PRV_S
|| (state
.prv
== PRV_S
&& sie
);
268 // M-ints have highest priority; consider S-ints only if no M-ints pending
269 if (enabled_interrupts
== 0)
270 enabled_interrupts
= pending_interrupts
& state
.mideleg
& -s_enabled
;
272 if (state
.dcsr
.cause
== 0 && enabled_interrupts
) {
273 // nonstandard interrupts have highest priority
274 if (enabled_interrupts
>> IRQ_M_EXT
)
275 enabled_interrupts
= enabled_interrupts
>> IRQ_M_EXT
<< IRQ_M_EXT
;
276 // external interrupts have next-highest priority
277 else if (enabled_interrupts
& (MIP_MEIP
| MIP_SEIP
))
278 enabled_interrupts
= enabled_interrupts
& (MIP_MEIP
| MIP_SEIP
);
279 // software interrupts have next-highest priority
280 else if (enabled_interrupts
& (MIP_MSIP
| MIP_SSIP
))
281 enabled_interrupts
= enabled_interrupts
& (MIP_MSIP
| MIP_SSIP
);
282 // timer interrupts have next-highest priority
283 else if (enabled_interrupts
& (MIP_MTIP
| MIP_STIP
))
284 enabled_interrupts
= enabled_interrupts
& (MIP_MTIP
| MIP_STIP
);
288 throw trap_t(((reg_t
)1 << (max_xlen
-1)) | ctz(enabled_interrupts
));
292 static int xlen_to_uxl(int xlen
)
301 reg_t
processor_t::legalize_privilege(reg_t prv
)
303 assert(prv
<= PRV_M
);
305 if (!supports_extension('U'))
308 if (prv
== PRV_H
|| !supports_extension('S'))
314 void processor_t::set_privilege(reg_t prv
)
317 state
.prv
= legalize_privilege(prv
);
320 void processor_t::enter_debug_mode(uint8_t cause
)
322 state
.dcsr
.cause
= cause
;
323 state
.dcsr
.prv
= state
.prv
;
324 set_privilege(PRV_M
);
325 state
.dpc
= state
.pc
;
326 state
.pc
= DEBUG_ROM_ENTRY
;
329 void processor_t::take_trap(trap_t
& t
, reg_t epc
)
332 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
335 fprintf(stderr
, "core %3d: tval 0x%016" PRIx64
"\n", id
,
339 if (state
.dcsr
.cause
) {
340 if (t
.cause() == CAUSE_BREAKPOINT
) {
341 state
.pc
= DEBUG_ROM_ENTRY
;
343 state
.pc
= DEBUG_ROM_TVEC
;
348 if (t
.cause() == CAUSE_BREAKPOINT
&& (
349 (state
.prv
== PRV_M
&& state
.dcsr
.ebreakm
) ||
350 (state
.prv
== PRV_S
&& state
.dcsr
.ebreaks
) ||
351 (state
.prv
== PRV_U
&& state
.dcsr
.ebreaku
))) {
352 enter_debug_mode(DCSR_CAUSE_SWBP
);
356 // by default, trap to M-mode, unless delegated to S-mode
357 reg_t bit
= t
.cause();
358 reg_t deleg
= state
.medeleg
;
359 reg_t svstate
= get_csr(CSR_SV_STATE
);
360 bool interrupt
= (bit
& ((reg_t
)1 << (max_xlen
-1))) != 0;
362 deleg
= state
.mideleg
, bit
&= ~((reg_t
)1 << (max_xlen
-1));
363 if (state
.prv
<= PRV_S
&& bit
< max_xlen
&& ((deleg
>> bit
) & 1)) {
364 // handle the trap in S-mode
365 state
.pc
= state
.stvec
;
366 state
.scause
= t
.cause();
368 state
.sesvstate
= svstate
;
369 state
.stval
= t
.get_tval();
371 reg_t s
= state
.mstatus
;
372 s
= set_field(s
, MSTATUS_SPIE
, get_field(s
, MSTATUS_SIE
));
373 s
= set_field(s
, MSTATUS_SPP
, state
.prv
);
374 s
= set_field(s
, MSTATUS_SIE
, 0);
375 set_csr(CSR_MSTATUS
, s
);
376 set_privilege(PRV_S
);
378 reg_t vector
= (state
.mtvec
& 1) && interrupt
? 4*bit
: 0;
379 state
.pc
= (state
.mtvec
& ~(reg_t
)1) + vector
;
381 state
.mesvstate
= svstate
;
382 state
.mcause
= t
.cause();
383 state
.mtval
= t
.get_tval();
385 reg_t s
= state
.mstatus
;
386 s
= set_field(s
, MSTATUS_MPIE
, get_field(s
, MSTATUS_MIE
));
387 s
= set_field(s
, MSTATUS_MPP
, state
.prv
);
388 s
= set_field(s
, MSTATUS_MIE
, 0);
389 set_csr(CSR_MSTATUS
, s
);
390 set_privilege(PRV_M
);
394 void processor_t::disasm(insn_t insn
)
396 uint64_t bits
= insn
.bits() & ((1ULL << (8 * insn_length(insn
.bits()))) - 1);
397 if (last_pc
!= state
.pc
|| last_bits
!= bits
) {
398 if (executions
!= 1) {
399 fprintf(stderr
, "core %3d: Executed %" PRIx64
" times\n", id
, executions
);
402 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx64
") %s\n",
403 id
, state
.pc
, bits
, disassembler
->disassemble(insn
).c_str());
412 int processor_t::paddr_bits()
414 assert(xlen
== max_xlen
);
415 return max_xlen
== 64 ? 50 : 34;
418 void state_t::get_csr_start_end(int &start
, int &end
)
420 start
= sv().state_bank
* 4;
421 end
= start
+ (1 << (sv().state_size
+1));
422 start
= std::min(sv_csr_sz(), start
);
423 end
= std::min(sv_csr_sz(), end
);
424 fprintf(stderr
, "sv state csr start/end: %d %d\n", start
, end
);
427 void state_t::sv_csr_reg_unpack()
429 // okaaay and now "unpack" the CAM to make it easier to use. this
430 // approach is not designed to be efficient right now. optimise later
431 // first clear the old tables
432 memset(sv().sv_int_tb
, 0, sizeof(sv().sv_int_tb
));
433 memset(sv().sv_fp_tb
, 0, sizeof(sv().sv_fp_tb
));
434 // now walk the CAM and unpack it
437 get_csr_start_end(start
, end
);
438 for (int i
= start
; i
< end
; i
++)
440 union sv_reg_csr_entry
*c
= &sv().sv_csrs
[i
];
441 uint64_t idx
= c
->b
.regkey
;
447 // XXX damn. this basically duplicates sv_insn_t::get_regentry.
450 r
= &sv().sv_int_tb
[idx
];
454 r
= &sv().sv_fp_tb
[idx
];
456 r
->elwidth
= c
->b
.elwidth
;
457 r
->regidx
= c
->b
.regidx
;
458 r
->isvec
= c
->b
.isvec
;
460 fprintf(stderr
, "setting REGCFG type:%d isvec:%d %d %d\n",
461 c
->b
.type
, r
->isvec
, (int)idx
, (int)r
->regidx
);
465 void state_t::sv_csr_pred_unpack()
467 memset(sv().sv_pred_int_tb
, 0, sizeof(sv().sv_pred_int_tb
));
468 memset(sv().sv_pred_fp_tb
, 0, sizeof(sv().sv_pred_fp_tb
));
471 get_csr_start_end(start
, end
);
472 for (int i
= start
; i
< end
; i
++)
474 union sv_pred_csr_entry
*c
= &sv().sv_pred_csrs
[i
];
475 uint64_t idx
= c
->b
.regkey
;
481 // XXX damn. this basically duplicates sv_insn_t::get_predentry.
484 r
= &sv().sv_pred_int_tb
[idx
];
488 r
= &sv().sv_pred_fp_tb
[idx
];
490 r
->regidx
= c
->b
.regidx
;
493 r
->ffirst
= c
->b
.ffirst
;
495 fprintf(stderr
, "setting PREDCFG %d type:%d zero:%d %d %d\n",
496 i
, c
->b
.type
, r
->zero
, (int)idx
, (int)r
->regidx
);
500 reg_t
processor_t::set_csr(int which
, reg_t val
, bool imm_mode
)
502 reg_t old_val
= get_csr(which
);
503 val
= _zext_xlen(val
);
504 reg_t delegable_ints
= MIP_SSIP
| MIP_STIP
| MIP_SEIP
505 | ((ext
!= NULL
) << IRQ_COP
);
506 reg_t all_ints
= delegable_ints
| MIP_MSIP
| MIP_MTIP
;
507 fprintf(stderr
, "set CSR %x %lx\n", which
, val
);
512 state
.sv().mvl
= std::min(val
+1, (uint64_t)64); // limited to XLEN width
513 old_val
= state
.sv().mvl
- 1;
514 // TODO XXX throw exception if val == 0
515 fprintf(stderr
, "set MVL %lx\n", state
.sv().mvl
);
519 // bits 0-5: mvl - 6-11: vl - 12-17: srcoffs - 18-23: destoffs
520 set_csr(CSR_SV_MVL
, get_field(val
, SV_STATE_VL
));
521 set_csr(CSR_SV_VL
, get_field(val
, SV_STATE_MVL
));
522 set_csr(CSR_SV_SUBVL
, get_field(val
, SV_STATE_SUBVL
)+1);
523 // decode (and limit) src/dest VL offsets
524 reg_t srcoffs
= get_field(val
, SV_STATE_SRCOFFS
);
525 reg_t destoffs
= get_field(val
, SV_STATE_DESTOFFS
);
526 state
.sv().srcoffs
= std::min(srcoffs
, state
.sv().vl
-1);
527 state
.sv().destoffs
= std::min(destoffs
, state
.sv().vl
-1);
528 // decode (and limit) src/dest SUBVL offsets
529 reg_t subdestoffs
= get_field(val
, SV_STATE_DSVOFFS
);
530 state
.sv().dsvoffs
= std::min(subdestoffs
, state
.sv().subvl
-1);
531 //int state_bank = get_field(val, SV_STATE_BANK);
532 //int state_size = get_field(val, SV_STATE_SIZE);
533 //set_csr(CSR_USVCFG, state_bank | (state_size << 3));
538 int old_bank
= state
.sv().state_bank
;
539 int old_size
= state
.sv().state_size
;
540 state
.sv().state_bank
= get_field(val
, SV_CFG_BANK
);
541 state
.sv().state_size
= get_field(val
, SV_CFG_SIZE
);
542 if (old_bank
!= state
.sv().state_bank
||
543 old_size
!= state
.sv().state_size
)
545 // if the bank or size is changed, the csrs that are enabled
546 // also changes. easiest thing in software: recalculate them all
547 state
.sv_csr_pred_unpack();
548 state
.sv_csr_reg_unpack();
553 state
.sv().subvl
= std::max(1, std::min(4, (int)val
));
554 old_val
= state
.sv().subvl
;
555 // TODO XXX throw exception if val attempted to be set == 0
556 fprintf(stderr
, "set SUBVL %lx\n", state
.sv().subvl
);
559 state
.sv().vl
= std::min(state
.sv().mvl
, val
+ 1);
560 old_val
= state
.sv().mvl
- 1;
561 // TODO XXX throw exception if val == 0
562 fprintf(stderr
, "set VL %lx\n", state
.sv().vl
);
567 bool top
= (which
== CSR_SVREGTOP
);
568 uint64_t v
= (uint64_t)val
;
569 fprintf(stderr
, "set SVREG %d %lx\n", top
, v
);
572 state
.get_csr_start_end(start
, end
);
573 uint64_t res_old
= 0;
574 int num_entries
= val
& 0xf;
575 int max_xlen_entries
= (xlen
== 64) ? 4 : 2;
577 num_entries
= max_xlen_entries
;
579 // read 2 16-bit entries for RV32, 4 16-bit entries for RV64
581 for (int i
= 0; i
< num_entries
; i
++) {
584 uint64_t mask
= 0xffffUL
<< (i
*16UL);
585 svcfg
= get_field(v
, mask
);
586 fprintf(stderr
, "SVREG mask %lx cfg %lx\n", mask
, svcfg
);
587 if (!svcfg
&& i
> 0) {
591 // see regpush on how this works.
592 uint64_t res
= state
.sv().regpush(svcfg
, end
, top
);
594 res_old
|= res
<< (popidx
* 16UL);
596 if (popidx
== max_xlen_entries
) {
602 state
.sv_csr_reg_unpack();
614 // comments removed as it's near-identical to the regs version
616 uint64_t v
= (uint64_t)val
;
617 int tbidx
= (which
- CSR_SVPREDCFG0
) * 2;
618 fprintf(stderr
, "set PREDCFG %d %lx\n", tbidx
, v
);
619 state
.sv().sv_pred_csrs
[tbidx
].u
= get_field(v
, 0xffff);
620 state
.sv().sv_pred_csrs
[tbidx
+1].u
= get_field(v
, 0xffff0000);
624 state
.sv().sv_pred_csrs
[tbidx
+2].u
= get_field(v
, 0xffffUL
<<32);
625 state
.sv().sv_pred_csrs
[tbidx
+3].u
= get_field(v
, 0xffffUL
<<48);
628 for (int i
= tbidx
+clroffset
; i
< 16; i
++)
630 state
.sv().sv_pred_csrs
[i
].u
= 0;
632 state
.sv_csr_pred_unpack();
637 state
.remap
[0].regidx
= get_field(val
, SV_REMAP_REGIDX0
);
638 state
.remap
[1].regidx
= get_field(val
, SV_REMAP_REGIDX1
);
639 state
.remap
[2].regidx
= get_field(val
, SV_REMAP_REGIDX2
);
640 state
.remap
[0].pred
= get_field(val
, SV_REMAP_PRED0
);
641 state
.remap
[1].pred
= get_field(val
, SV_REMAP_PRED1
);
642 state
.remap
[2].pred
= get_field(val
, SV_REMAP_PRED2
);
643 state
.remap
[0].shape
= get_field(val
, SV_REMAP_SHAPE0
);
644 state
.remap
[1].shape
= get_field(val
, SV_REMAP_SHAPE1
);
645 state
.remap
[2].shape
= get_field(val
, SV_REMAP_SHAPE2
);
652 int shapeidx
= which
- CSR_USHAPE0
;
653 state
.shape
[shapeidx
].xsz
= get_field(val
, SV_SHAPE_XDIM
) + 1;
654 state
.shape
[shapeidx
].ysz
= get_field(val
, SV_SHAPE_YDIM
) + 1;
655 state
.shape
[shapeidx
].zsz
= get_field(val
, SV_SHAPE_ZDIM
) + 1;
656 state
.shape
[shapeidx
].offs
= (get_field(val
, (1<<7 )) ? 0x1 : 0) |
657 (get_field(val
, (1<<15)) ? 0x2 : 0) |
658 (get_field(val
, (1<<23)) ? 0x4 : 0);
659 state
.shape
[shapeidx
].permute
= get_field(val
, SV_SHAPE_PERM
);
660 state
.shape
[shapeidx
].setup_map();
661 fprintf(stderr
, "sv shape %d x %d y %d z %d offs %d perm %d\n",
663 state
.shape
[shapeidx
].xsz
,
664 state
.shape
[shapeidx
].ysz
,
665 state
.shape
[shapeidx
].zsz
,
666 state
.shape
[shapeidx
].offs
,
667 state
.shape
[shapeidx
].permute
);
673 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
677 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
681 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
682 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
685 if ((val
^ state
.mstatus
) &
686 (MSTATUS_MPP
| MSTATUS_MPRV
| MSTATUS_SUM
| MSTATUS_MXR
))
689 reg_t mask
= MSTATUS_SIE
| MSTATUS_SPIE
| MSTATUS_MIE
| MSTATUS_MPIE
690 | MSTATUS_FS
| MSTATUS_MPRV
| MSTATUS_SUM
691 | MSTATUS_MXR
| MSTATUS_TW
| MSTATUS_TVM
692 | MSTATUS_TSR
| MSTATUS_UXL
| MSTATUS_SXL
|
693 (ext
? MSTATUS_XS
: 0);
695 reg_t requested_mpp
= legalize_privilege(get_field(val
, MSTATUS_MPP
));
696 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_MPP
, requested_mpp
);
697 if (supports_extension('S'))
700 state
.mstatus
= (state
.mstatus
& ~mask
) | (val
& mask
);
702 bool dirty
= (state
.mstatus
& MSTATUS_FS
) == MSTATUS_FS
;
703 dirty
|= (state
.mstatus
& MSTATUS_XS
) == MSTATUS_XS
;
705 state
.mstatus
= set_field(state
.mstatus
, MSTATUS32_SD
, dirty
);
707 state
.mstatus
= set_field(state
.mstatus
, MSTATUS64_SD
, dirty
);
709 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_UXL
, xlen_to_uxl(max_xlen
));
710 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_UXL
, xlen_to_uxl(max_xlen
));
711 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_SXL
, xlen_to_uxl(max_xlen
));
712 // U-XLEN == S-XLEN == M-XLEN
717 reg_t mask
= MIP_SSIP
| MIP_STIP
;
718 state
.mip
= (state
.mip
& ~mask
) | (val
& mask
);
722 state
.mie
= (state
.mie
& ~all_ints
) | (val
& all_ints
);
725 state
.mideleg
= (state
.mideleg
& ~delegable_ints
) | (val
& delegable_ints
);
729 (1 << CAUSE_MISALIGNED_FETCH
) |
730 (1 << CAUSE_BREAKPOINT
) |
731 (1 << CAUSE_USER_ECALL
) |
732 (1 << CAUSE_FETCH_PAGE_FAULT
) |
733 (1 << CAUSE_LOAD_PAGE_FAULT
) |
734 (1 << CAUSE_STORE_PAGE_FAULT
);
735 state
.medeleg
= (state
.medeleg
& ~mask
) | (val
& mask
);
741 state
.minstret
= (state
.minstret
>> 32 << 32) | (val
& 0xffffffffU
);
743 state
.minstret
= val
;
744 // The ISA mandates that if an instruction writes instret, the write
745 // takes precedence over the increment to instret. However, Spike
746 // unconditionally increments instret after executing an instruction.
747 // Correct for this artifact by decrementing instret here.
752 state
.minstret
= (val
<< 32) | (state
.minstret
<< 32 >> 32);
753 state
.minstret
--; // See comment above.
756 state
.scounteren
= val
;
759 state
.mcounteren
= val
;
762 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
763 | SSTATUS_XS
| SSTATUS_SUM
| SSTATUS_MXR
;
764 return set_csr(CSR_MSTATUS
, (state
.mstatus
& ~mask
) | (val
& mask
));
767 reg_t mask
= MIP_SSIP
& state
.mideleg
;
768 return set_csr(CSR_MIP
, (state
.mip
& ~mask
) | (val
& mask
));
771 return set_csr(CSR_MIE
,
772 (state
.mie
& ~state
.mideleg
) | (val
& state
.mideleg
));
776 state
.satp
= val
& (SATP32_PPN
| SATP32_MODE
);
777 if (max_xlen
== 64 && (get_field(val
, SATP64_MODE
) == SATP_MODE_OFF
||
778 get_field(val
, SATP64_MODE
) == SATP_MODE_SV39
||
779 get_field(val
, SATP64_MODE
) == SATP_MODE_SV48
))
780 state
.satp
= val
& (SATP64_PPN
| SATP64_MODE
);
783 case CSR_SEPC
: state
.sepc
= val
& ~(reg_t
)1; break;
784 case CSR_SESVSTATE
: state
.sesvstate
= val
; break;
785 case CSR_STVEC
: state
.stvec
= val
>> 2 << 2; break;
786 case CSR_SSCRATCH
: state
.sscratch
= val
; break;
787 case CSR_SCAUSE
: state
.scause
= val
; break;
788 case CSR_STVAL
: state
.stval
= val
; break;
789 case CSR_MEPC
: state
.mepc
= val
& ~(reg_t
)1; break;
790 case CSR_MESVSTATE
: state
.mesvstate
= val
; break;
791 case CSR_MTVEC
: state
.mtvec
= val
& ~(reg_t
)2; break;
792 case CSR_MSCRATCH
: state
.mscratch
= val
; break;
793 case CSR_MCAUSE
: state
.mcause
= val
; break;
794 case CSR_MTVAL
: state
.mtval
= val
; break;
796 // the write is ignored if increasing IALIGN would misalign the PC
797 if (!(val
& (1L << ('C' - 'A'))) && (state
.pc
& 2))
800 if (!(val
& (1L << ('F' - 'A'))))
801 val
&= ~(1L << ('D' - 'A'));
803 // allow MAFDC bits in MISA to be modified
805 mask
|= 1L << ('M' - 'A');
806 mask
|= 1L << ('A' - 'A');
807 mask
|= 1L << ('F' - 'A');
808 mask
|= 1L << ('D' - 'A');
809 mask
|= 1L << ('C' - 'A');
812 state
.misa
= (val
& mask
) | (state
.misa
& ~mask
);
816 if (val
< state
.num_triggers
) {
822 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
823 if (mc
->dmode
&& !state
.dcsr
.cause
) {
826 mc
->dmode
= get_field(val
, MCONTROL_DMODE(xlen
));
827 mc
->select
= get_field(val
, MCONTROL_SELECT
);
828 mc
->timing
= get_field(val
, MCONTROL_TIMING
);
829 mc
->action
= (mcontrol_action_t
) get_field(val
, MCONTROL_ACTION
);
830 mc
->chain
= get_field(val
, MCONTROL_CHAIN
);
831 mc
->match
= (mcontrol_match_t
) get_field(val
, MCONTROL_MATCH
);
832 mc
->m
= get_field(val
, MCONTROL_M
);
833 mc
->h
= get_field(val
, MCONTROL_H
);
834 mc
->s
= get_field(val
, MCONTROL_S
);
835 mc
->u
= get_field(val
, MCONTROL_U
);
836 mc
->execute
= get_field(val
, MCONTROL_EXECUTE
);
837 mc
->store
= get_field(val
, MCONTROL_STORE
);
838 mc
->load
= get_field(val
, MCONTROL_LOAD
);
839 // Assume we're here because of csrw.
846 if (state
.mcontrol
[state
.tselect
].dmode
&& !state
.dcsr
.cause
) {
849 if (state
.tselect
< state
.num_triggers
) {
850 state
.tdata2
[state
.tselect
] = val
;
854 state
.dcsr
.prv
= get_field(val
, DCSR_PRV
);
855 state
.dcsr
.step
= get_field(val
, DCSR_STEP
);
856 // TODO: ndreset and fullreset
857 state
.dcsr
.ebreakm
= get_field(val
, DCSR_EBREAKM
);
858 state
.dcsr
.ebreakh
= get_field(val
, DCSR_EBREAKH
);
859 state
.dcsr
.ebreaks
= get_field(val
, DCSR_EBREAKS
);
860 state
.dcsr
.ebreaku
= get_field(val
, DCSR_EBREAKU
);
861 state
.dcsr
.halt
= get_field(val
, DCSR_HALT
);
864 state
.dpc
= val
& ~(reg_t
)1;
867 state
.dscratch
= val
;
873 reg_t
processor_t::get_csr(int which
)
875 uint32_t ctr_en
= -1;
876 if (state
.prv
< PRV_M
)
877 ctr_en
&= state
.mcounteren
;
878 if (state
.prv
< PRV_S
)
879 ctr_en
&= state
.scounteren
;
880 bool ctr_ok
= (ctr_en
>> (which
& 31)) & 1;
883 if (which
>= CSR_HPMCOUNTER3
&& which
<= CSR_HPMCOUNTER31
)
885 if (xlen
== 32 && which
>= CSR_HPMCOUNTER3H
&& which
<= CSR_HPMCOUNTER31H
)
888 if (which
>= CSR_MHPMCOUNTER3
&& which
<= CSR_MHPMCOUNTER31
)
890 if (xlen
== 32 && which
>= CSR_MHPMCOUNTER3H
&& which
<= CSR_MHPMCOUNTER31H
)
892 if (which
>= CSR_MHPMEVENT3
&& which
<= CSR_MHPMEVENT31
)
899 return state
.sv().vl
;
901 return (state
.sv().state_bank
) | (state
.sv().state_size
<<3);
903 fprintf(stderr
, "get CSR_SV_STATE vl %ld mvl %ld subvl %ld\n",
907 return ((std::max((int)state
.sv().vl
, 1))-1) |
908 ((std::max((int)state
.sv().mvl
, 1)-1)<<6) |
909 (state
.sv().srcoffs
<<12) |
910 (state
.sv().destoffs
<<18) |
911 ((std::max((int)state
.sv().subvl
, 1)-1)<<24) |
912 (state
.sv().dsvoffs
<<26);
914 return state
.sv().mvl
;
916 return state
.sv().subvl
;
919 return 0;// XXX TODO: return correct entry
928 return 0;// XXX TODO: return correct entry
930 return 0;// XXX TODO: return correct entry
934 return 0;// XXX TODO: return correct entry
938 if (!supports_extension('F'))
943 if (!supports_extension('F'))
948 if (!supports_extension('F'))
950 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
954 return state
.minstret
;
958 return state
.minstret
;
961 if (ctr_ok
&& xlen
== 32)
962 return state
.minstret
>> 32;
967 return state
.minstret
>> 32;
969 case CSR_SCOUNTEREN
: return state
.scounteren
;
970 case CSR_MCOUNTEREN
: return state
.mcounteren
;
972 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
973 | SSTATUS_XS
| SSTATUS_SUM
| SSTATUS_MXR
| SSTATUS_UXL
;
974 reg_t sstatus
= state
.mstatus
& mask
;
975 if ((sstatus
& SSTATUS_FS
) == SSTATUS_FS
||
976 (sstatus
& SSTATUS_XS
) == SSTATUS_XS
)
977 sstatus
|= (xlen
== 32 ? SSTATUS32_SD
: SSTATUS64_SD
);
980 case CSR_SIP
: return state
.mip
& state
.mideleg
;
981 case CSR_SIE
: return state
.mie
& state
.mideleg
;
982 case CSR_SEPC
: return state
.sepc
& pc_alignment_mask();
983 case CSR_SESVSTATE
: return state
.sesvstate
;
984 case CSR_STVAL
: return state
.stval
;
985 case CSR_STVEC
: return state
.stvec
;
988 return state
.scause
| ((state
.scause
>> (max_xlen
-1)) << (xlen
-1));
991 if (get_field(state
.mstatus
, MSTATUS_TVM
))
992 require_privilege(PRV_M
);
994 case CSR_SSCRATCH
: return state
.sscratch
;
995 case CSR_MSTATUS
: return state
.mstatus
;
996 case CSR_MIP
: return state
.mip
;
997 case CSR_MIE
: return state
.mie
;
998 case CSR_MEPC
: return state
.mepc
& pc_alignment_mask();
999 case CSR_MESVSTATE
: return state
.mesvstate
;
1000 case CSR_MSCRATCH
: return state
.mscratch
;
1001 case CSR_MCAUSE
: return state
.mcause
;
1002 case CSR_MTVAL
: return state
.mtval
;
1003 case CSR_MISA
: return state
.misa
;
1004 case CSR_MARCHID
: return 0;
1005 case CSR_MIMPID
: return 0;
1006 case CSR_MVENDORID
: return 0;
1007 case CSR_MHARTID
: return id
;
1008 case CSR_MTVEC
: return state
.mtvec
;
1009 case CSR_MEDELEG
: return state
.medeleg
;
1010 case CSR_MIDELEG
: return state
.mideleg
;
1011 case CSR_TSELECT
: return state
.tselect
;
1013 if (state
.tselect
< state
.num_triggers
) {
1015 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
1016 v
= set_field(v
, MCONTROL_TYPE(xlen
), mc
->type
);
1017 v
= set_field(v
, MCONTROL_DMODE(xlen
), mc
->dmode
);
1018 v
= set_field(v
, MCONTROL_MASKMAX(xlen
), mc
->maskmax
);
1019 v
= set_field(v
, MCONTROL_SELECT
, mc
->select
);
1020 v
= set_field(v
, MCONTROL_TIMING
, mc
->timing
);
1021 v
= set_field(v
, MCONTROL_ACTION
, mc
->action
);
1022 v
= set_field(v
, MCONTROL_CHAIN
, mc
->chain
);
1023 v
= set_field(v
, MCONTROL_MATCH
, mc
->match
);
1024 v
= set_field(v
, MCONTROL_M
, mc
->m
);
1025 v
= set_field(v
, MCONTROL_H
, mc
->h
);
1026 v
= set_field(v
, MCONTROL_S
, mc
->s
);
1027 v
= set_field(v
, MCONTROL_U
, mc
->u
);
1028 v
= set_field(v
, MCONTROL_EXECUTE
, mc
->execute
);
1029 v
= set_field(v
, MCONTROL_STORE
, mc
->store
);
1030 v
= set_field(v
, MCONTROL_LOAD
, mc
->load
);
1037 if (state
.tselect
< state
.num_triggers
) {
1038 return state
.tdata2
[state
.tselect
];
1043 case CSR_TDATA3
: return 0;
1047 v
= set_field(v
, DCSR_XDEBUGVER
, 1);
1048 v
= set_field(v
, DCSR_EBREAKM
, state
.dcsr
.ebreakm
);
1049 v
= set_field(v
, DCSR_EBREAKH
, state
.dcsr
.ebreakh
);
1050 v
= set_field(v
, DCSR_EBREAKS
, state
.dcsr
.ebreaks
);
1051 v
= set_field(v
, DCSR_EBREAKU
, state
.dcsr
.ebreaku
);
1052 v
= set_field(v
, DCSR_STOPCYCLE
, 0);
1053 v
= set_field(v
, DCSR_STOPTIME
, 0);
1054 v
= set_field(v
, DCSR_CAUSE
, state
.dcsr
.cause
);
1055 v
= set_field(v
, DCSR_STEP
, state
.dcsr
.step
);
1056 v
= set_field(v
, DCSR_PRV
, state
.dcsr
.prv
);
1060 return state
.dpc
& pc_alignment_mask();
1062 return state
.dscratch
;
1064 throw trap_illegal_instruction(0);
1067 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
1069 throw trap_illegal_instruction(0);
1072 insn_func_t
processor_t::decode_insn(insn_t insn
)
1074 // look up opcode in hash table
1075 size_t idx
= insn
.bits() % OPCODE_CACHE_SIZE
;
1076 insn_desc_t desc
= opcode_cache
[idx
];
1078 if (unlikely(insn
.bits() != desc
.match
)) {
1079 // fall back to linear search
1080 insn_desc_t
* p
= &instructions
[0];
1081 while ((insn
.bits() & p
->mask
) != p
->match
)
1085 if (p
->mask
!= 0 && p
> &instructions
[0]) {
1086 if (p
->match
!= (p
-1)->match
&& p
->match
!= (p
+1)->match
) {
1087 // move to front of opcode list to reduce miss penalty
1088 while (--p
>= &instructions
[0])
1090 instructions
[0] = desc
;
1094 opcode_cache
[idx
] = desc
;
1095 opcode_cache
[idx
].match
= insn
.bits();
1098 return xlen
== 64 ? desc
.rv64
: desc
.rv32
;
1101 void processor_t::register_insn(insn_desc_t desc
)
1103 instructions
.push_back(desc
);
1106 void processor_t::build_opcode_map()
1109 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
1110 if (lhs
.match
== rhs
.match
)
1111 return lhs
.mask
> rhs
.mask
;
1112 return lhs
.match
> rhs
.match
;
1115 std::sort(instructions
.begin(), instructions
.end(), cmp());
1117 for (size_t i
= 0; i
< OPCODE_CACHE_SIZE
; i
++)
1118 opcode_cache
[i
] = {0, 0, &illegal_instruction
, &illegal_instruction
};
1121 void processor_t::register_extension(extension_t
* x
)
1123 for (auto insn
: x
->get_instructions())
1124 register_insn(insn
);
1126 for (auto disasm_insn
: x
->get_disasms())
1127 disassembler
->add_insn(disasm_insn
);
1129 throw std::logic_error("only one extension may be registered");
1131 x
->set_processor(this);
1134 void processor_t::register_base_instructions()
1136 #define DECLARE_INSN(name, match, mask) \
1137 insn_bits_t name##_match = (match), name##_mask = (mask);
1138 #include "encoding.h"
1141 #define DEFINE_INSN(name) \
1142 REGISTER_INSN(this, name, name##_match, name##_mask)
1143 #include "insn_list.h"
1146 register_insn({0, 0, &illegal_instruction
, &illegal_instruction
});
1150 bool processor_t::load(reg_t addr
, size_t len
, uint8_t* bytes
)
1156 memset(bytes
, 0, len
);
1157 bytes
[0] = get_field(state
.mip
, MIP_MSIP
);
1166 bool processor_t::store(reg_t addr
, size_t len
, const uint8_t* bytes
)
1172 state
.mip
= set_field(state
.mip
, MIP_MSIP
, bytes
[0]);
1181 void processor_t::trigger_updated()
1184 mmu
->check_triggers_fetch
= false;
1185 mmu
->check_triggers_load
= false;
1186 mmu
->check_triggers_store
= false;
1188 for (unsigned i
= 0; i
< state
.num_triggers
; i
++) {
1189 if (state
.mcontrol
[i
].execute
) {
1190 mmu
->check_triggers_fetch
= true;
1192 if (state
.mcontrol
[i
].load
) {
1193 mmu
->check_triggers_load
= true;
1195 if (state
.mcontrol
[i
].store
) {
1196 mmu
->check_triggers_store
= true;