11 #include "softfloat.h"
12 #include "platform.h" // softfloat isNaNF32UI, etc.
13 #include "internals.h" // ditto
15 processor_t::processor_t(sim_t
* _sim
, char* _mem
, size_t _memsz
)
16 : sim(_sim
), mmu(_mem
,_memsz
)
18 memset(XPR
,0,sizeof(XPR
));
19 memset(FPR
,0,sizeof(FPR
));
31 set_sr(SR_S
| SR_SX
); // SX ignored if 64b mode not supported
34 memset(counters
,0,sizeof(counters
));
44 for (int i
=0; i
<MAX_UTS
; i
++)
47 // a few assumptions about endianness, including freg_t union
48 static_assert(BYTE_ORDER
== LITTLE_ENDIAN
);
49 static_assert(sizeof(freg_t
) == 8);
50 static_assert(sizeof(reg_t
) == 8);
52 static_assert(sizeof(insn_t
) == 4);
53 static_assert(sizeof(uint128_t
) == 16 && sizeof(int128_t
) == 16);
58 processor_t::~processor_t()
63 void processor_t::init(uint32_t _id
)
67 for (int i
=0; i
<MAX_UTS
; i
++)
69 uts
[i
] = new processor_t(sim
, mmu
.mem
, mmu
.memsz
);
71 uts
[i
]->set_sr(uts
[i
]->sr
| SR_EF
);
72 uts
[i
]->set_sr(uts
[i
]->sr
| SR_EV
);
76 #ifdef RISCV_ENABLE_ICSIM
77 icsim
= new icsim_t(1024, 1, 32);
81 void processor_t::set_sr(uint32_t val
)
84 #ifndef RISCV_ENABLE_64BIT
85 sr
&= ~(SR_SX
| SR_UX
);
87 #ifndef RISCV_ENABLE_FPU
90 #ifndef RISCV_ENABLE_RVC
93 #ifndef RISCV_ENABLE_VEC
97 xprlen
= ((sr
& SR_S
) ? (sr
& SR_SX
) : (sr
& SR_UX
)) ? 64 : 32;
100 void processor_t::set_fsr(uint32_t val
)
102 fsr
= val
& ~FSR_ZERO
;
105 void processor_t::vcfg()
107 if (nxpr_use
== 0 && nfpr_use
== 0)
109 else if (nfpr_use
== 0)
110 vlmax
= (nxpr_all
-1) / (nxpr_use
-1);
111 else if (nxpr_use
== 0)
112 vlmax
= (nfpr_all
-1) / (nfpr_use
-1);
114 vlmax
= std::min((nxpr_all
-1) / (nxpr_use
-1), (nfpr_all
-1) / (nfpr_use
-1));
116 vlmax
= std::min(vlmax
, MAX_UTS
);
119 void processor_t::setvl(int vlapp
)
121 vl
= std::min(vlmax
, vlapp
);
124 void processor_t::step(size_t n
, bool noisy
)
131 uint32_t interrupts
= (cause
& CAUSE_IP
) >> CAUSE_IP_SHIFT
;
132 interrupts
&= (sr
& SR_IM
) >> SR_IM_SHIFT
;
133 if(interrupts
&& (sr
& SR_ET
))
134 take_trap(trap_interrupt
,noisy
);
136 insn_t insn
= mmu
.load_insn(pc
, sr
& SR_EC
);
137 #ifdef RISCV_ENABLE_ICSIM
138 icsim
->tick(pc
, insn_length(insn
));
141 reg_t npc
= pc
+ insn_length(insn
);
151 if(count
++ == compare
)
152 cause
|= 1 << (TIMER_IRQ
+CAUSE_IP_SHIFT
);
161 catch(vt_command_t cmd
)
163 if (cmd
== vt_command_stop
)
168 void processor_t::take_trap(trap_t t
, bool noisy
)
170 demand(t
< NUM_TRAPS
, "internal error: bad trap number %d", int(t
));
171 demand(sr
& SR_ET
, "error mode on core %d!\ntrap %s, pc 0x%016llx",
172 id
, trap_name(t
), (unsigned long long)pc
);
174 printf("core %3d: trap %s, pc 0x%016llx\n",
175 id
, trap_name(t
), (unsigned long long)pc
);
177 set_sr((((sr
& ~SR_ET
) | SR_S
) & ~SR_PS
) | ((sr
& SR_S
) ? SR_PS
: 0));
178 cause
= (cause
& ~CAUSE_EXCCODE
) | (t
<< CAUSE_EXCCODE_SHIFT
);
181 badvaddr
= mmu
.get_badvaddr();
184 void processor_t::disasm(insn_t insn
, reg_t pc
)
186 printf("core %3d: 0x%016llx (0x%08x) ",id
,(unsigned long long)pc
,insn
.bits
);
188 #ifdef RISCV_HAVE_LIBOPCODES
189 disassemble_info info
;
190 INIT_DISASSEMBLE_INFO(info
, stdout
, fprintf
);
191 info
.flavour
= bfd_target_unknown_flavour
;
192 info
.arch
= bfd_arch_mips
;
193 info
.mach
= 101; // XXX bfd_mach_mips_riscv requires modified bfd.h
194 info
.endian
= BFD_ENDIAN_LITTLE
;
195 info
.buffer
= (bfd_byte
*)&insn
;
196 info
.buffer_length
= sizeof(insn
);
197 info
.buffer_vma
= pc
;
199 int ret
= print_insn_little_mips(pc
, &info
);
200 demand(ret
== (INSN_IS_RVC(insn
.bits
) ? 2 : 4), "disasm bug!");