1 // See LICENSE for license details.
15 processor_t::processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
)
16 : sim(*_sim
), mmu(*_mmu
), id(_id
), utidx(0)
20 // create microthreads
21 for (int i
=0; i
<MAX_UTS
; i
++)
22 uts
[i
] = new processor_t(&sim
, &mmu
, id
, i
);
25 processor_t::processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
,
27 : sim(*_sim
), mmu(*_mmu
), id(_id
)
30 set_pcr(PCR_SR
, SR_U64
| SR_EF
| SR_EV
);
33 // microthreads don't possess their own microthreads
34 for (int i
=0; i
<MAX_UTS
; i
++)
38 processor_t::~processor_t()
42 void processor_t::reset(bool value
)
48 // the ISA guarantees on boot that the PC is 0x2000 and the the processor
49 // is in supervisor mode, and in 64-bit mode, if supported, with traps
50 // and virtual memory disabled.
52 set_pcr(PCR_SR
, SR_S
| SR_S64
| SR_IM
);
55 // the following state is undefined upon boot-up,
56 // but we zero it for determinism
82 void processor_t::set_fsr(uint32_t val
)
84 fsr
= val
& ~FSR_ZERO
; // clear FSR bits that read as zero
87 void processor_t::vcfg()
89 if (nxpr_use
+ nfpr_use
< 2)
90 vlmax
= nxfpr_bank
* vecbanks_count
;
92 vlmax
= (nxfpr_bank
/ (nxpr_use
+ nfpr_use
- 1)) * vecbanks_count
;
94 vlmax
= std::min(vlmax
, MAX_UTS
);
97 void processor_t::setvl(int vlapp
)
99 vl
= std::min(vlmax
, vlapp
);
102 void processor_t::take_interrupt()
104 uint32_t interrupts
= (sr
& SR_IP
) >> SR_IP_SHIFT
;
105 interrupts
&= (sr
& SR_IM
) >> SR_IM_SHIFT
;
107 if(interrupts
&& (sr
& SR_ET
))
108 for(int i
= 0; ; i
++, interrupts
>>= 1)
110 throw interrupt_t(i
);
113 void processor_t::step(size_t n
, bool noisy
)
126 // execute_insn fetches and executes one instruction
127 #define execute_insn(noisy) \
129 mmu_t::insn_fetch_t fetch = _mmu.load_insn(npc, sr & SR_EC); \
130 if(noisy) disasm(fetch.insn, npc); \
131 npc = fetch.func(this, fetch.insn, npc); \
135 if(noisy
) for( ; i
< n
; i
++) // print out instructions as we go
139 // unrolled for speed
140 for( ; n
> 3 && i
< n
-3; i
+=4)
153 // an exception occurred in the target processor
158 take_trap((1ULL << (8*sizeof(reg_t
)-1)) + t
.i
, noisy
);
160 catch(vt_command_t cmd
)
162 // this microthread has finished
163 assert(cmd
== vt_command_stop
);
168 // update timer and possibly register a timer interrupt
169 uint32_t old_count
= count
;
171 if(old_count
< compare
&& uint64_t(old_count
) + i
>= compare
)
172 set_interrupt(IRQ_TIMER
, true);
175 void processor_t::take_trap(reg_t t
, bool noisy
)
180 printf("core %3d: interrupt %d, epc 0x%016" PRIx64
"\n",
183 printf("core %3d: trap %s, epc 0x%016" PRIx64
"\n",
184 id
, trap_name(trap_t(t
)), pc
);
187 // switch to supervisor, set previous supervisor bit, disable traps
188 set_pcr(PCR_SR
, (((sr
& ~SR_ET
) | SR_S
) & ~SR_PS
) | ((sr
& SR_S
) ? SR_PS
: 0));
192 badvaddr
= mmu
.get_badvaddr();
195 void processor_t::deliver_ipi()
198 set_pcr(PCR_CLR_IPI
, 1);
201 void processor_t::disasm(insn_t insn
, reg_t pc
)
203 // the disassembler is stateless, so we share it
204 static disassembler disasm
;
205 printf("core %3d: 0x%016" PRIx64
" (0x%08" PRIx32
") %s\n",
206 id
, pc
, insn
.bits
, disasm
.disassemble(insn
).c_str());
209 void processor_t::set_pcr(int which
, reg_t val
)
214 sr
= (val
& ~SR_IP
) | (sr
& SR_IP
);
215 #ifndef RISCV_ENABLE_64BIT
216 sr
&= ~(SR_S64
| SR_U64
);
218 #ifndef RISCV_ENABLE_FPU
221 #ifndef RISCV_ENABLE_RVC
224 #ifndef RISCV_ENABLE_VEC
240 set_interrupt(IRQ_TIMER
, false);
250 set_interrupt(IRQ_IPI
, val
& 1);
259 vecbanks
= val
& 0xff;
260 vecbanks_count
= __builtin_popcountll(vecbanks
);
267 set_interrupt(IRQ_HOST
, val
!= 0);
273 reg_t
processor_t::get_pcr(int which
)
292 return mmu
.get_ptbr();
304 return nfpr_use
<< 18 | nxpr_use
<< 12 | vl
;
313 void processor_t::set_interrupt(int which
, bool on
)
315 uint32_t mask
= (1 << (which
+ SR_IP_SHIFT
)) & SR_IP
;