riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "htif.h"
  10 #include "disasm.h"
  11 #include "gdbserver.h"
  12 #include <cinttypes>
  13 #include <cmath>
  14 #include <cstdlib>
  15 #include <iostream>
  16 #include <assert.h>
  17 #include <limits.h>
  18 #include <stdexcept>
  19 #include <algorithm>
  20
  21 #undef STATE
  22 #define STATE state
  23
  24 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  25         bool halt_on_reset)
  26   : debug(false), sim(sim), ext(NULL), disassembler(new disassembler_t),
  27     id(id), run(false), halt_on_reset(halt_on_reset)
  28 {
  29   parse_isa_string(isa);
  30
  31   mmu = new mmu_t(sim, this);
  32
  33   reset(true);
  34
  35   register_base_instructions();
  36 }
  37
  38 processor_t::~processor_t()
  39 {
  40 #ifdef RISCV_ENABLE_HISTOGRAM
  41   if (histogram_enabled)
  42   {
  43     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  44     for (auto it : pc_histogram)
  45       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  46   }
  47 #endif
  48
  49   delete mmu;
  50   delete disassembler;
  51 }
  52
  53 static void bad_isa_string(const char* isa)
  54 {
  55   fprintf(stderr, "error: bad --isa option %s\n", isa);
  56   abort();
  57 }
  58
  59 void processor_t::parse_isa_string(const char* str)
  60 {
  61   std::string lowercase, tmp;
  62   for (const char *r = str; *r; r++)
  63     lowercase += std::tolower(*r);
  64
  65   const char* p = lowercase.c_str();
  66   const char* all_subsets = "imafdc";
  67
  68   max_xlen = 64;
  69   isa = reg_t(2) << 62;
  70
  71   if (strncmp(p, "rv32", 4) == 0)
  72     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  73   else if (strncmp(p, "rv64", 4) == 0)
  74     p += 4;
  75   else if (strncmp(p, "rv", 2) == 0)
  76     p += 2;
  77
  78   if (!*p) {
  79     p = all_subsets;
  80   } else if (*p == 'g') { // treat "G" as "IMAFD"
  81     tmp = std::string("imafd") + (p+1);
  82     p = &tmp[0];
  83   } else if (*p != 'i') {
  84     bad_isa_string(str);
  85   }
  86
  87   isa_string = "rv" + std::to_string(max_xlen) + p;
  88   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  89
  90   while (*p) {
  91     isa |= 1L << (*p - 'a');
  92
  93     if (auto next = strchr(all_subsets, *p)) {
  94       all_subsets = next + 1;
  95       p++;
  96     } else if (*p == 'x') {
  97       const char* ext = p+1, *end = ext;
  98       while (islower(*end))
  99         end++;
 100       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 101       p = end;
 102     } else {
 103       bad_isa_string(str);
 104     }
 105   }
 106
 107   if (supports_extension('D') && !supports_extension('F'))
 108     bad_isa_string(str);
 109
 110   // advertise support for supervisor and user modes
 111   isa |= 1L << ('s' - 'a');
 112   isa |= 1L << ('u' - 'a');
 113 }
 114
 115 void state_t::reset()
 116 {
 117   memset(this, 0, sizeof(*this));
 118   prv = PRV_M;
 119   pc = DEFAULT_RSTVEC;
 120   mtvec = DEFAULT_MTVEC;
 121   load_reservation = -1;
 122 }
 123
 124 void processor_t::set_debug(bool value)
 125 {
 126   debug = value;
 127   if (ext)
 128     ext->set_debug(value);
 129 }
 130
 131 void processor_t::set_histogram(bool value)
 132 {
 133   histogram_enabled = value;
 134 #ifndef RISCV_ENABLE_HISTOGRAM
 135   if (value) {
 136     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 137     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 138   }
 139 #endif
 140 }
 141
 142 void processor_t::reset(bool value)
 143 {
 144   if (run == !value)
 145     return;
 146   run = !value;
 147
 148   state.reset();
 149   state.dcsr.halt = halt_on_reset;
 150   halt_on_reset = false;
 151   set_csr(CSR_MSTATUS, state.mstatus);
 152
 153   if (ext)
 154     ext->reset(); // reset the extension
 155 }
 156
 157 void processor_t::raise_interrupt(reg_t which)
 158 {
 159   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 160 }
 161
 162 static int ctz(reg_t val)
 163 {
 164   int res = 0;
 165   if (val)
 166     while ((val & 1) == 0)
 167       val >>= 1, res++;
 168   return res;
 169 }
 170
 171 void processor_t::take_interrupt()
 172 {
 173   reg_t pending_interrupts = state.mip & state.mie;
 174
 175   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 176   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 177   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 178
 179   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 180   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 181   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 182
 183   if (enabled_interrupts)
 184     raise_interrupt(ctz(enabled_interrupts));
 185 }
 186
 187 static bool validate_priv(reg_t priv)
 188 {
 189   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 190 }
 191
 192 void processor_t::set_privilege(reg_t prv)
 193 {
 194   assert(validate_priv(prv));
 195   mmu->flush_tlb();
 196   state.prv = prv;
 197 }
 198
 199 void processor_t::enter_debug_mode(uint8_t cause)
 200 {
 201   fprintf(stderr, "enter_debug_mode(%d), mstatus=0x%lx, prv=0x%lx\n", cause, state.mstatus, state.prv);
 202   state.dcsr.cause = cause;
 203   state.dcsr.prv = state.prv;
 204   set_privilege(PRV_M);
 205   state.dpc = state.pc;
 206   state.pc = DEBUG_ROM_START;
 207   debug = true; // TODO
 208 }
 209
 210 void processor_t::take_trap(trap_t& t, reg_t epc)
 211 {
 212   if (debug) {
 213     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 214             id, t.name(), epc);
 215     if (t.has_badaddr())
 216       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 217           t.get_badaddr());
 218   }
 219
 220   if (t.cause() == CAUSE_BREAKPOINT &&
 221           sim->gdbserver && sim->gdbserver->connected()) {
 222     enter_debug_mode(DCSR_CAUSE_SWBP);
 223     return;
 224   }
 225
 226   // by default, trap to M-mode, unless delegated to S-mode
 227   reg_t bit = t.cause();
 228   reg_t deleg = state.medeleg;
 229   if (bit & ((reg_t)1 << (max_xlen-1)))
 230     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 231   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 232     // handle the trap in S-mode
 233     state.pc = state.stvec;
 234     state.scause = t.cause();
 235     state.sepc = epc;
 236     if (t.has_badaddr())
 237       state.sbadaddr = t.get_badaddr();
 238
 239     reg_t s = state.mstatus;
 240     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 241     s = set_field(s, MSTATUS_SPP, state.prv);
 242     s = set_field(s, MSTATUS_SIE, 0);
 243     set_csr(CSR_MSTATUS, s);
 244     set_privilege(PRV_S);
 245   } else {
 246     if (state.dcsr.cause) {
 247       state.pc = DEBUG_ROM_EXCEPTION;
 248     } else {
 249       state.pc = state.mtvec;
 250     }
 251     state.mcause = t.cause();
 252     state.mepc = epc;
 253     if (t.has_badaddr())
 254       state.mbadaddr = t.get_badaddr();
 255
 256     reg_t s = state.mstatus;
 257     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 258     s = set_field(s, MSTATUS_MPP, state.prv);
 259     s = set_field(s, MSTATUS_MIE, 0);
 260     set_csr(CSR_MSTATUS, s);
 261     set_privilege(PRV_M);
 262   }
 263
 264   yield_load_reservation();
 265 }
 266
 267 void processor_t::disasm(insn_t insn)
 268 {
 269   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 270   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 271           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 272 }
 273
 274 static bool validate_vm(int max_xlen, reg_t vm)
 275 {
 276   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 277     return true;
 278   if (max_xlen == 32 && vm == VM_SV32)
 279     return true;
 280   return vm == VM_MBARE;
 281 }
 282
 283 void processor_t::set_csr(int which, reg_t val)
 284 {
 285   val = zext_xlen(val);
 286   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 287   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 288   switch (which)
 289   {
 290     case CSR_FFLAGS:
 291       dirty_fp_state;
 292       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 293       break;
 294     case CSR_FRM:
 295       dirty_fp_state;
 296       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 297       break;
 298     case CSR_FCSR:
 299       dirty_fp_state;
 300       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 301       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 302       break;
 303     case CSR_MSTATUS: {
 304       if ((val ^ state.mstatus) &
 305           (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM))
 306         mmu->flush_tlb();
 307
 308       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 309                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 310                  | (ext ? MSTATUS_XS : 0);
 311
 312       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 313         mask |= MSTATUS_VM;
 314       if (validate_priv(get_field(val, MSTATUS_MPP)))
 315         mask |= MSTATUS_MPP;
 316
 317       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 318
 319       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 320       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 321       if (max_xlen == 32)
 322         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 323       else
 324         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 325
 326       // spike supports the notion of xlen < max_xlen, but current priv spec
 327       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 328       xlen = max_xlen;
 329       break;
 330     }
 331     case CSR_MIP: {
 332       reg_t mask = MIP_SSIP | MIP_STIP;
 333       state.mip = (state.mip & ~mask) | (val & mask);
 334       break;
 335     }
 336     case CSR_MIE:
 337       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 338       break;
 339     case CSR_MIDELEG:
 340       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 341       break;
 342     case CSR_MEDELEG: {
 343       reg_t mask = 0;
 344 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 345 #include "encoding.h"
 346 #undef DECLARE_CAUSE
 347       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 348       break;
 349     }
 350     case CSR_MUCOUNTEREN:
 351       state.mucounteren = val & 7;
 352       break;
 353     case CSR_MSCOUNTEREN:
 354       state.mscounteren = val & 7;
 355       break;
 356     case CSR_SSTATUS: {
 357       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 358                  | SSTATUS_XS | SSTATUS_PUM;
 359       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 360     }
 361     case CSR_SIP:
 362       return set_csr(CSR_MIP,
 363                      (state.mip & ~state.mideleg) | (val & state.mideleg));
 364     case CSR_SIE:
 365       return set_csr(CSR_MIE,
 366                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 367     case CSR_SEPC: state.sepc = val; break;
 368     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 369     case CSR_SPTBR: state.sptbr = val; break;
 370     case CSR_SSCRATCH: state.sscratch = val; break;
 371     case CSR_SCAUSE: state.scause = val; break;
 372     case CSR_SBADADDR: state.sbadaddr = val; break;
 373     case CSR_MEPC: state.mepc = val; break;
 374     case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
 375     case CSR_MSCRATCH: state.mscratch = val; break;
 376     case CSR_MCAUSE: state.mcause = val; break;
 377     case CSR_MBADADDR: state.mbadaddr = val; break;
 378     case DCSR_ADDRESS:
 379       // TODO: Use get_field style
 380       state.dcsr.prv = (val & DCSR_PRV_MASK) >> DCSR_PRV_OFFSET;
 381       state.dcsr.step = (val & DCSR_STEP_MASK) >> DCSR_STEP_OFFSET;
 382       // TODO: ndreset and fullreset
 383       state.dcsr.ebreakm = (val & DCSR_EBREAKM_MASK) >> DCSR_EBREAKM_OFFSET;
 384       state.dcsr.ebreakh = (val & DCSR_EBREAKH_MASK) >> DCSR_EBREAKH_OFFSET;
 385       state.dcsr.ebreaks = (val & DCSR_EBREAKS_MASK) >> DCSR_EBREAKS_OFFSET;
 386       state.dcsr.ebreaku = (val & DCSR_EBREAKU_MASK) >> DCSR_EBREAKU_OFFSET;
 387       state.dcsr.halt = (val & DCSR_HALT_MASK) >> DCSR_HALT_OFFSET;
 388       break;
 389     case DPC_ADDRESS:
 390       state.dpc = val;
 391       break;
 392     case DSCRATCH_ADDRESS:
 393       state.dscratch = val;
 394       break;
 395   }
 396 }
 397
 398 reg_t processor_t::get_csr(int which)
 399 {
 400   switch (which)
 401   {
 402     case CSR_FFLAGS:
 403       require_fp;
 404       if (!supports_extension('F'))
 405         break;
 406       return state.fflags;
 407     case CSR_FRM:
 408       require_fp;
 409       if (!supports_extension('F'))
 410         break;
 411       return state.frm;
 412     case CSR_FCSR:
 413       require_fp;
 414       if (!supports_extension('F'))
 415         break;
 416       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 417     case CSR_TIME:
 418     case CSR_INSTRET:
 419     case CSR_CYCLE:
 420       if ((state.mucounteren >> (which & (xlen-1))) & 1)
 421         return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
 422       break;
 423     case CSR_STIME:
 424     case CSR_SINSTRET:
 425     case CSR_SCYCLE:
 426       if ((state.mscounteren >> (which & (xlen-1))) & 1)
 427         return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
 428       break;
 429     case CSR_MUCOUNTEREN: return state.mucounteren;
 430     case CSR_MSCOUNTEREN: return state.mscounteren;
 431     case CSR_MUCYCLE_DELTA: return 0;
 432     case CSR_MUTIME_DELTA: return 0;
 433     case CSR_MUINSTRET_DELTA: return 0;
 434     case CSR_MSCYCLE_DELTA: return 0;
 435     case CSR_MSTIME_DELTA: return 0;
 436     case CSR_MSINSTRET_DELTA: return 0;
 437     case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 438     case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
 439     case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 440     case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
 441     case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
 442     case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
 443     case CSR_MCYCLE: return state.minstret;
 444     case CSR_MINSTRET: return state.minstret;
 445     case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
 446     case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
 447     case CSR_SSTATUS: {
 448       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 449                  | SSTATUS_XS | SSTATUS_PUM;
 450       reg_t sstatus = state.mstatus & mask;
 451       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 452           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 453         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 454       return sstatus;
 455     }
 456     case CSR_SIP: return state.mip & state.mideleg;
 457     case CSR_SIE: return state.mie & state.mideleg;
 458     case CSR_SEPC: return state.sepc;
 459     case CSR_SBADADDR: return state.sbadaddr;
 460     case CSR_STVEC: return state.stvec;
 461     case CSR_SCAUSE:
 462       if (max_xlen > xlen)
 463         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 464       return state.scause;
 465     case CSR_SPTBR: return state.sptbr;
 466     case CSR_SASID: return 0;
 467     case CSR_SSCRATCH: return state.sscratch;
 468     case CSR_MSTATUS: return state.mstatus;
 469     case CSR_MIP: return state.mip;
 470     case CSR_MIE: return state.mie;
 471     case CSR_MEPC: return state.mepc;
 472     case CSR_MSCRATCH: return state.mscratch;
 473     case CSR_MCAUSE: return state.mcause;
 474     case CSR_MBADADDR: return state.mbadaddr;
 475     case CSR_MISA: return isa;
 476     case CSR_MARCHID: return 0;
 477     case CSR_MIMPID: return 0;
 478     case CSR_MVENDORID: return 0;
 479     case CSR_MHARTID: return id;
 480     case CSR_MTVEC: return state.mtvec;
 481     case CSR_MEDELEG: return state.medeleg;
 482     case CSR_MIDELEG: return state.mideleg;
 483     case DCSR_ADDRESS:
 484       {
 485         uint32_t value =
 486           (1 << DCSR_XDEBUGVER_OFFSET) |
 487           (0 << DCSR_HWBPCOUNT_OFFSET) |
 488           (0 << DCSR_NDRESET_OFFSET) |
 489           (0 << DCSR_FULLRESET_OFFSET) |
 490           (state.dcsr.prv << DCSR_PRV_OFFSET) |
 491           (state.dcsr.step << DCSR_STEP_OFFSET) |
 492           (sim->debug_module.get_interrupt(id) << DCSR_DEBUGINT_OFFSET) |
 493           (0 << DCSR_STOPCYCLE_OFFSET) |
 494           (0 << DCSR_STOPTIME_OFFSET) |
 495           (state.dcsr.ebreakm << DCSR_EBREAKM_OFFSET) |
 496           (state.dcsr.ebreakh << DCSR_EBREAKH_OFFSET) |
 497           (state.dcsr.ebreaks << DCSR_EBREAKS_OFFSET) |
 498           (state.dcsr.ebreaku << DCSR_EBREAKU_OFFSET) |
 499           (state.dcsr.halt << DCSR_HALT_OFFSET) |
 500           (state.dcsr.cause << DCSR_CAUSE_OFFSET);
 501         return value;
 502       }
 503     case DPC_ADDRESS:
 504       return state.dpc;
 505     case DSCRATCH_ADDRESS:
 506       return state.dscratch;
 507   }
 508   throw trap_illegal_instruction();
 509 }
 510
 511 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 512 {
 513   throw trap_illegal_instruction();
 514 }
 515
 516 insn_func_t processor_t::decode_insn(insn_t insn)
 517 {
 518   // look up opcode in hash table
 519   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 520   insn_desc_t desc = opcode_cache[idx];
 521
 522   if (unlikely(insn.bits() != desc.match)) {
 523     // fall back to linear search
 524     insn_desc_t* p = &instructions[0];
 525     while ((insn.bits() & p->mask) != p->match)
 526       p++;
 527     desc = *p;
 528
 529     if (p->mask != 0 && p > &instructions[0]) {
 530       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 531         // move to front of opcode list to reduce miss penalty
 532         while (--p >= &instructions[0])
 533           *(p+1) = *p;
 534         instructions[0] = desc;
 535       }
 536     }
 537
 538     opcode_cache[idx] = desc;
 539     opcode_cache[idx].match = insn.bits();
 540   }
 541
 542   return xlen == 64 ? desc.rv64 : desc.rv32;
 543 }
 544
 545 void processor_t::register_insn(insn_desc_t desc)
 546 {
 547   instructions.push_back(desc);
 548 }
 549
 550 void processor_t::build_opcode_map()
 551 {
 552   struct cmp {
 553     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 554       if (lhs.match == rhs.match)
 555         return lhs.mask > rhs.mask;
 556       return lhs.match > rhs.match;
 557     }
 558   };
 559   std::sort(instructions.begin(), instructions.end(), cmp());
 560
 561   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 562     opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
 563 }
 564
 565 void processor_t::register_extension(extension_t* x)
 566 {
 567   for (auto insn : x->get_instructions())
 568     register_insn(insn);
 569   build_opcode_map();
 570   for (auto disasm_insn : x->get_disasms())
 571     disassembler->add_insn(disasm_insn);
 572   if (ext != NULL)
 573     throw std::logic_error("only one extension may be registered");
 574   ext = x;
 575   x->set_processor(this);
 576 }
 577
 578 void processor_t::register_base_instructions()
 579 {
 580   #define DECLARE_INSN(name, match, mask) \
 581     insn_bits_t name##_match = (match), name##_mask = (mask);
 582   #include "encoding.h"
 583   #undef DECLARE_INSN
 584
 585   #define DEFINE_INSN(name) \
 586     REGISTER_INSN(this, name, name##_match, name##_mask)
 587   #include "insn_list.h"
 588   #undef DEFINE_INSN
 589
 590   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 591   build_opcode_map();
 592 }
 593
 594 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 595 {
 596   return false;
 597 }
 598
 599 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 600 {
 601   switch (addr)
 602   {
 603     case 0:
 604       state.mip &= ~MIP_MSIP;
 605       if (bytes[0] & 1)
 606         state.mip |= MIP_MSIP;
 607       return true;
 608
 609     default:
 610       return false;
 611   }
 612 }