riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "htif.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
  23   : sim(sim), ext(NULL), disassembler(new disassembler_t),
  24     id(id), run(false), debug(false)
  25 {
  26   parse_isa_string(isa);
  27
  28   mmu = new mmu_t(sim->mem, sim->memsz);
  29   mmu->set_processor(this);
  30
  31   reset(true);
  32
  33   register_base_instructions();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   cpuid = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, cpuid = 0, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa = "rv" + std::to_string(max_xlen) + p;
  86   cpuid |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87
  88   while (*p) {
  89     cpuid |= 1L << (*p - 'a');
  90
  91     if (auto next = strchr(all_subsets, *p)) {
  92       all_subsets = next + 1;
  93       p++;
  94     } else if (*p == 'x') {
  95       const char* ext = p+1, *end = ext;
  96       while (islower(*end))
  97         end++;
  98       register_extension(find_extension(std::string(ext, end - ext).c_str())());
  99       p = end;
 100     } else {
 101       bad_isa_string(str);
 102     }
 103   }
 104
 105   if (supports_extension('D') && !supports_extension('F'))
 106     bad_isa_string(str);
 107 }
 108
 109 void state_t::reset()
 110 {
 111   memset(this, 0, sizeof(*this));
 112   prv = PRV_M;
 113   pc = DEFAULT_MTVEC + 0x100;
 114   load_reservation = -1;
 115 }
 116
 117 void processor_t::set_debug(bool value)
 118 {
 119   debug = value;
 120   if (ext)
 121     ext->set_debug(value);
 122 }
 123
 124 void processor_t::set_histogram(bool value)
 125 {
 126   histogram_enabled = value;
 127 #ifndef RISCV_ENABLE_HISTOGRAM
 128   if (value) {
 129     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 130     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 131   }
 132 #endif
 133 }
 134
 135 void processor_t::reset(bool value)
 136 {
 137   if (run == !value)
 138     return;
 139   run = !value;
 140
 141   state.reset();
 142   set_csr(CSR_MSTATUS, state.mstatus);
 143
 144   if (ext)
 145     ext->reset(); // reset the extension
 146 }
 147
 148 void processor_t::raise_interrupt(reg_t which)
 149 {
 150   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 151 }
 152
 153 static int ctz(reg_t val)
 154 {
 155   int res = 0;
 156   if (val)
 157     while ((val & 1) == 0)
 158       val >>= 1, res++;
 159   return res;
 160 }
 161
 162 void processor_t::take_interrupt()
 163 {
 164   reg_t interrupts = state.mip & state.mie;
 165
 166   reg_t m_interrupts = interrupts & ~state.mideleg;
 167   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 168   if ((state.prv < PRV_M || (state.prv == PRV_M && mie)) && m_interrupts)
 169     raise_interrupt(ctz(m_interrupts));
 170
 171   reg_t s_interrupts = interrupts & state.mideleg;
 172   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 173   if ((state.prv < PRV_S || (state.prv == PRV_S && sie)) && s_interrupts)
 174     raise_interrupt(ctz(s_interrupts));
 175 }
 176
 177 void processor_t::check_timer()
 178 {
 179   if (sim->rtc >= state.mtimecmp)
 180     state.mip |= MIP_MTIP;
 181 }
 182
 183 static bool validate_priv(reg_t priv)
 184 {
 185   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 186 }
 187
 188 void processor_t::set_privilege(reg_t prv)
 189 {
 190   assert(validate_priv(prv));
 191   mmu->flush_tlb();
 192   state.prv = prv;
 193 }
 194
 195 void processor_t::take_trap(trap_t& t, reg_t epc)
 196 {
 197   if (debug)
 198     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 199             id, t.name(), epc);
 200
 201   // by default, trap to M-mode, unless delegated to S-mode
 202   reg_t bit = t.cause();
 203   reg_t deleg = state.medeleg;
 204   if (bit & ((reg_t)1 << (max_xlen-1)))
 205     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 206   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 207     // handle the trap in S-mode
 208     state.pc = state.stvec;
 209     state.scause = t.cause();
 210     state.sepc = epc;
 211     if (t.has_badaddr())
 212       state.sbadaddr = t.get_badaddr();
 213
 214     reg_t s = state.mstatus;
 215     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 216     s = set_field(s, MSTATUS_SPP, state.prv);
 217     s = set_field(s, MSTATUS_SIE, 0);
 218     set_csr(CSR_MSTATUS, s);
 219     set_privilege(PRV_S);
 220   } else {
 221     state.pc = DEFAULT_MTVEC + 0x40 * state.prv;
 222     state.mcause = t.cause();
 223     state.mepc = epc;
 224     if (t.has_badaddr())
 225       state.mbadaddr = t.get_badaddr();
 226
 227     reg_t s = state.mstatus;
 228     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 229     s = set_field(s, MSTATUS_MPP, state.prv);
 230     s = set_field(s, MSTATUS_MIE, 0);
 231     set_csr(CSR_MSTATUS, s);
 232     set_privilege(PRV_M);
 233   }
 234
 235   yield_load_reservation();
 236 }
 237
 238 void processor_t::disasm(insn_t insn)
 239 {
 240   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 241   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 242           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 243 }
 244
 245 static bool validate_vm(int max_xlen, reg_t vm)
 246 {
 247   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 248     return true;
 249   if (max_xlen == 32 && vm == VM_SV32)
 250     return true;
 251   return vm == VM_MBARE;
 252 }
 253
 254 void processor_t::set_csr(int which, reg_t val)
 255 {
 256   reg_t all_ints = MIP_SSIP | MIP_MSIP | MIP_STIP | MIP_MTIP | (1UL << IRQ_HOST);
 257   reg_t s_ints = MIP_SSIP | MIP_STIP;
 258   switch (which)
 259   {
 260     case CSR_FFLAGS:
 261       dirty_fp_state;
 262       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 263       break;
 264     case CSR_FRM:
 265       dirty_fp_state;
 266       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 267       break;
 268     case CSR_FCSR:
 269       dirty_fp_state;
 270       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 271       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 272       break;
 273     case CSR_MTIME:
 274     case CSR_STIMEW:
 275       // this implementation ignores writes to MTIME
 276       break;
 277     case CSR_MTIMEH:
 278     case CSR_STIMEHW:
 279       // this implementation ignores writes to MTIME
 280       break;
 281     case CSR_TIMEW:
 282       val -= sim->rtc;
 283       if (xlen == 32)
 284         state.sutime_delta = (uint32_t)val | (state.sutime_delta >> 32 << 32);
 285       else
 286         state.sutime_delta = val;
 287       break;
 288     case CSR_TIMEHW:
 289       val = ((val << 32) - sim->rtc) >> 32;
 290       state.sutime_delta = (val << 32) | (uint32_t)state.sutime_delta;
 291       break;
 292     case CSR_CYCLEW:
 293     case CSR_INSTRETW:
 294       val -= state.minstret;
 295       if (xlen == 32)
 296         state.suinstret_delta = (uint32_t)val | (state.suinstret_delta >> 32 << 32);
 297       else
 298         state.suinstret_delta = val;
 299       break;
 300     case CSR_CYCLEHW:
 301     case CSR_INSTRETHW:
 302       val = ((val << 32) - state.minstret) >> 32;
 303       state.suinstret_delta = (val << 32) | (uint32_t)state.suinstret_delta;
 304       break;
 305     case CSR_MSTATUS: {
 306       if ((val ^ state.mstatus) & (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV))
 307         mmu->flush_tlb();
 308
 309       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 310                  | MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_FS
 311                  | (ext ? MSTATUS_XS : 0);
 312
 313       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 314         mask |= MSTATUS_VM;
 315       if (validate_priv(get_field(val, MSTATUS_MPP)))
 316         mask |= MSTATUS_MPP;
 317
 318       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 319
 320       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 321       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 322       if (max_xlen == 32)
 323         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 324       else
 325         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 326
 327       // spike supports the notion of xlen < max_xlen, but current priv spec
 328       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 329       xlen = max_xlen;
 330       break;
 331     }
 332     case CSR_MIP: {
 333       reg_t mask = all_ints &~ MIP_MTIP;
 334       state.mip = (state.mip & ~mask) | (val & mask);
 335       break;
 336     }
 337     case CSR_MIPI:
 338       state.mip = set_field(state.mip, MIP_MSIP, val & 1);
 339       break;
 340     case CSR_MIE:
 341       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 342       break;
 343     case CSR_MIDELEG:
 344       state.mideleg = (state.mideleg & ~s_ints) | (val & s_ints);
 345       break;
 346     case CSR_MEDELEG: {
 347       reg_t mask = 0;
 348 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 349 #include "encoding.h"
 350 #undef DECLARE_CAUSE
 351       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 352       break;
 353     }
 354     case CSR_SSTATUS: {
 355       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 356                  | SSTATUS_XS;
 357       set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 358       break;
 359     }
 360     case CSR_SIP: {
 361       reg_t mask = s_ints &~ MIP_STIP;
 362       state.mip = (state.mip & ~mask) | (val & mask);
 363       break;
 364     }
 365     case CSR_SIE: {
 366       reg_t mask = s_ints;
 367       state.mie = (state.mie & ~mask) | (val & mask);
 368       break;
 369     }
 370     case CSR_SEPC: state.sepc = val; break;
 371     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 372     case CSR_SPTBR: state.sptbr = zext_xlen(val & -PGSIZE); break;
 373     case CSR_SSCRATCH: state.sscratch = val; break;
 374     case CSR_SCAUSE: state.scause = val; break;
 375     case CSR_SBADADDR: state.sbadaddr = val; break;
 376     case CSR_MEPC: state.mepc = val; break;
 377     case CSR_MSCRATCH: state.mscratch = val; break;
 378     case CSR_MCAUSE: state.mcause = val; break;
 379     case CSR_MBADADDR: state.mbadaddr = val; break;
 380     case CSR_MTIMECMP:
 381       state.mip &= ~MIP_MTIP;
 382       state.mtimecmp = val;
 383       break;
 384     case CSR_MTOHOST:
 385       if (state.tohost == 0)
 386         state.tohost = val;
 387       break;
 388     case CSR_MFROMHOST:
 389       state.mip = (state.mip & ~(1 << IRQ_HOST)) | (val ? (1 << IRQ_HOST) : 0);
 390       state.fromhost = val;
 391       break;
 392   }
 393 }
 394
 395 reg_t processor_t::get_csr(int which)
 396 {
 397   switch (which)
 398   {
 399     case CSR_FFLAGS:
 400       require_fp;
 401       if (!supports_extension('F'))
 402         break;
 403       return state.fflags;
 404     case CSR_FRM:
 405       require_fp;
 406       if (!supports_extension('F'))
 407         break;
 408       return state.frm;
 409     case CSR_FCSR:
 410       require_fp;
 411       if (!supports_extension('F'))
 412         break;
 413       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 414     case CSR_MTIME:
 415     case CSR_STIME:
 416     case CSR_STIMEW:
 417       return sim->rtc;
 418     case CSR_MTIMEH:
 419     case CSR_STIMEH:
 420     case CSR_STIMEHW:
 421       return sim->rtc >> 32;
 422     case CSR_TIME:
 423     case CSR_TIMEW:
 424       return sim->rtc + state.sutime_delta;
 425     case CSR_CYCLE:
 426     case CSR_CYCLEW:
 427     case CSR_INSTRET:
 428     case CSR_INSTRETW:
 429       return state.minstret + state.suinstret_delta;
 430     case CSR_TIMEH:
 431     case CSR_TIMEHW:
 432       if (xlen == 64)
 433         break;
 434       return (sim->rtc + state.sutime_delta) >> 32;
 435     case CSR_CYCLEH:
 436     case CSR_INSTRETH:
 437     case CSR_CYCLEHW:
 438     case CSR_INSTRETHW:
 439       if (xlen == 64)
 440         break;
 441       return (state.minstret + state.suinstret_delta) >> 32;
 442     case CSR_SSTATUS: {
 443       reg_t sstatus = state.mstatus &
 444         (SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS);
 445       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 446           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 447         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 448       return sstatus;
 449     }
 450     case CSR_SIP: return state.mip & (MIP_SSIP | MIP_STIP);
 451     case CSR_SIE: return state.mie & (MIP_SSIP | MIP_STIP);
 452     case CSR_SEPC: return state.sepc;
 453     case CSR_SBADADDR: return state.sbadaddr;
 454     case CSR_STVEC: return state.stvec;
 455     case CSR_SCAUSE:
 456       if (max_xlen > xlen)
 457         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 458       return state.scause;
 459     case CSR_SPTBR: return state.sptbr;
 460     case CSR_SASID: return 0;
 461     case CSR_SSCRATCH: return state.sscratch;
 462     case CSR_MSTATUS: return state.mstatus;
 463     case CSR_MIP: return state.mip;
 464     case CSR_MIPI: return 0;
 465     case CSR_MIE: return state.mie;
 466     case CSR_MEPC: return state.mepc;
 467     case CSR_MSCRATCH: return state.mscratch;
 468     case CSR_MCAUSE: return state.mcause;
 469     case CSR_MBADADDR: return state.mbadaddr;
 470     case CSR_MTIMECMP: return state.mtimecmp;
 471     case CSR_MCPUID: return cpuid;
 472     case CSR_MIMPID: return IMPL_ROCKET;
 473     case CSR_MHARTID: return id;
 474     case CSR_MTVEC: return DEFAULT_MTVEC;
 475     case CSR_MEDELEG: return state.medeleg;
 476     case CSR_MIDELEG: return state.mideleg;
 477     case CSR_MTOHOST:
 478       sim->get_htif()->tick(); // not necessary, but faster
 479       return state.tohost;
 480     case CSR_MFROMHOST:
 481       sim->get_htif()->tick(); // not necessary, but faster
 482       return state.fromhost;
 483     case CSR_MIOBASE: return sim->memsz;
 484     case CSR_UARCH0:
 485     case CSR_UARCH1:
 486     case CSR_UARCH2:
 487     case CSR_UARCH3:
 488     case CSR_UARCH4:
 489     case CSR_UARCH5:
 490     case CSR_UARCH6:
 491     case CSR_UARCH7:
 492     case CSR_UARCH8:
 493     case CSR_UARCH9:
 494     case CSR_UARCH10:
 495     case CSR_UARCH11:
 496     case CSR_UARCH12:
 497     case CSR_UARCH13:
 498     case CSR_UARCH14:
 499     case CSR_UARCH15:
 500       return 0;
 501   }
 502   throw trap_illegal_instruction();
 503 }
 504
 505 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 506 {
 507   throw trap_illegal_instruction();
 508 }
 509
 510 insn_func_t processor_t::decode_insn(insn_t insn)
 511 {
 512   // look up opcode in hash table
 513   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 514   insn_desc_t desc = opcode_cache[idx];
 515
 516   if (unlikely(insn.bits() != desc.match)) {
 517     // fall back to linear search
 518     insn_desc_t* p = &instructions[0];
 519     while ((insn.bits() & p->mask) != p->match)
 520       p++;
 521     desc = *p;
 522
 523     if (p->mask != 0 && p > &instructions[0]) {
 524       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 525         // move to front of opcode list to reduce miss penalty
 526         while (--p >= &instructions[0])
 527           *(p+1) = *p;
 528         instructions[0] = desc;
 529       }
 530     }
 531
 532     opcode_cache[idx] = desc;
 533     opcode_cache[idx].match = insn.bits();
 534   }
 535
 536   return xlen == 64 ? desc.rv64 : desc.rv32;
 537 }
 538
 539 void processor_t::register_insn(insn_desc_t desc)
 540 {
 541   instructions.push_back(desc);
 542 }
 543
 544 void processor_t::build_opcode_map()
 545 {
 546   struct cmp {
 547     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 548       if (lhs.match == rhs.match)
 549         return lhs.mask > rhs.mask;
 550       return lhs.match > rhs.match;
 551     }
 552   };
 553   std::sort(instructions.begin(), instructions.end(), cmp());
 554
 555   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 556     opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
 557 }
 558
 559 void processor_t::register_extension(extension_t* x)
 560 {
 561   for (auto insn : x->get_instructions())
 562     register_insn(insn);
 563   build_opcode_map();
 564   for (auto disasm_insn : x->get_disasms())
 565     disassembler->add_insn(disasm_insn);
 566   if (ext != NULL)
 567     throw std::logic_error("only one extension may be registered");
 568   ext = x;
 569   x->set_processor(this);
 570 }
 571
 572 void processor_t::register_base_instructions()
 573 {
 574   #define DECLARE_INSN(name, match, mask) \
 575     insn_bits_t name##_match = (match), name##_mask = (mask);
 576   #include "encoding.h"
 577   #undef DECLARE_INSN
 578
 579   #define DEFINE_INSN(name) \
 580     REGISTER_INSN(this, name, name##_match, name##_mask)
 581   #include "insn_list.h"
 582   #undef DEFINE_INSN
 583
 584   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 585   build_opcode_map();
 586 }
 587
 588 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 589 {
 590   try {
 591     auto res = get_csr(addr / (max_xlen / 8));
 592     memcpy(bytes, &res, len);
 593     return true;
 594   } catch (trap_illegal_instruction& t) {
 595     return false;
 596   }
 597 }
 598
 599 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 600 {
 601   try {
 602     reg_t value = 0;
 603     memcpy(&value, bytes, len);
 604     set_csr(addr / (max_xlen / 8), value);
 605     return true;
 606   } catch (trap_illegal_instruction& t) {
 607     return false;
 608   }
 609 }